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authorMaciej W. Rozycki <macro@codesourcery.com>2014-11-12 15:21:53 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2014-12-16 12:45:20 +0000
commit7215d7e7aea85699bf516c3e8d84f6a22584da35 (patch)
treeaff3ab7544db394ba03ee41a4eb54f671d59a3db /target-mips
parent81a423e6c6d3ccaa79de4e58024369c660c1eeb4 (diff)
downloadhqemu-7215d7e7aea85699bf516c3e8d84f6a22584da35.zip
hqemu-7215d7e7aea85699bf516c3e8d84f6a22584da35.tar.gz
target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP
Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by using register addition operations. This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands to tcg_gen_mov_tl whenever `rt' is 0 and `rs' is not, therefore copying `rs' to `rd' verbatim. This is not the case with OPC_ADDIU where a sign-extension from bit #31 is made, unless in the uninteresting case of `rs' being 0, losing the upper 32 bits of the value copied for any proper 64-bit values. This also serves as an optimization as one op is produced in generated code rather than two (again, unless `rs' is 0, where it doesn't change anything). Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index b5d5b39..1a275bf 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -13936,8 +13936,8 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx)
rs = rs_rt_enc[enc_rs];
rt = rs_rt_enc[enc_rt];
- gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0);
- gen_arith_imm(ctx, OPC_ADDIU, re, rt, 0);
+ gen_arith(ctx, OPC_ADDU, rd, rs, 0);
+ gen_arith(ctx, OPC_ADDU, re, rt, 0);
}
break;
case LBU16:
@@ -14018,7 +14018,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx)
int rd = uMIPS_RD5(ctx->opcode);
int rs = uMIPS_RS5(ctx->opcode);
- gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0);
+ gen_arith(ctx, OPC_ADDU, rd, rs, 0);
}
break;
case ANDI16:
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