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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-24 19:46:23 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-24 19:46:23 +0000
commite6bb7d7efd76a8aeed5300e72481646e4d2b4d7e (patch)
tree910c56c3da6917f06d75c1acf2aa92714a033acf /target-mips/op.c
parent2784847001ba054a2912460f9735fd4497327d02 (diff)
downloadhqemu-e6bb7d7efd76a8aeed5300e72481646e4d2b4d7e.zip
hqemu-e6bb7d7efd76a8aeed5300e72481646e4d2b4d7e.tar.gz
Fix mov[tf].ps handling for MIPS, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4563 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/op.c')
-rw-r--r--target-mips/op.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/target-mips/op.c b/target-mips/op.c
index 7e5b1a7..f09c2a4 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -1632,10 +1632,11 @@ FLOAT_OP(movf, s)
}
FLOAT_OP(movf, ps)
{
- if (!(env->fpu->fcr31 & PARAM1)) {
+ unsigned int mask = GET_FP_COND (env->fpu) >> PARAM1;
+ if (!(mask & 1))
WT2 = WT0;
+ if (!(mask & 2))
WTH2 = WTH0;
- }
DEBUG_FPU_STATE();
FORCE_RET();
}
@@ -1655,10 +1656,11 @@ FLOAT_OP(movt, s)
}
FLOAT_OP(movt, ps)
{
- if (env->fpu->fcr31 & PARAM1) {
+ unsigned int mask = GET_FP_COND (env->fpu) >> PARAM1;
+ if (mask & 1)
WT2 = WT0;
+ if (mask & 2)
WTH2 = WTH0;
- }
DEBUG_FPU_STATE();
FORCE_RET();
}
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