diff options
author | Richard Henderson <rth@twiddle.net> | 2013-01-23 16:10:49 -0800 |
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committer | Richard Henderson <rth@twiddle.net> | 2013-02-18 15:25:55 -0800 |
commit | db9f2597722d5d8bc5f2330f186288d893114338 (patch) | |
tree | 240c865992c49a148ba7df2e0d50dffa7cb04a88 /target-i386/translate.c | |
parent | 8601c0b6c553a018fc62007efa8ac2a71d77f449 (diff) | |
download | hqemu-db9f2597722d5d8bc5f2330f186288d893114338.zip hqemu-db9f2597722d5d8bc5f2330f186288d893114338.tar.gz |
target-i386: Make helper_cc_compute_{all,c} const
Pass the data in explicitly, rather than indirectly via env.
This avoids all sorts of unnecessary register spillage.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386/translate.c')
-rw-r--r-- | target-i386/translate.c | 31 |
1 files changed, 27 insertions, 4 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index 31e3442..5235aff 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -882,13 +882,37 @@ static void gen_op_update_neg_cc(void) /* compute all eflags to cc_src */ static void gen_compute_eflags(DisasContext *s) { + TCGv zero, dst, src1; + int live, dead; + if (s->cc_op == CC_OP_EFLAGS) { return; } + + TCGV_UNUSED(zero); + dst = cpu_cc_dst; + src1 = cpu_cc_src; + + /* Take care to not read values that are not live. */ + live = cc_op_live[s->cc_op] & ~USES_CC_SRCT; + dead = live ^ (USES_CC_DST | USES_CC_SRC); + if (dead) { + zero = tcg_const_tl(0); + if (dead & USES_CC_DST) { + dst = zero; + } + if (dead & USES_CC_SRC) { + src1 = zero; + } + } + gen_update_cc_op(s); - gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_env, cpu_cc_op); + gen_helper_cc_compute_all(cpu_cc_src, dst, src1, cpu_cc_op); set_cc_op(s, CC_OP_EFLAGS); - tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32); + + if (dead) { + tcg_temp_free(zero); + } } typedef struct CCPrepare { @@ -980,8 +1004,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) /* The need to compute only C from CC_OP_DYNAMIC is important in efficiently implementing e.g. INC at the start of a TB. */ gen_update_cc_op(s); - gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_env, cpu_cc_op); - tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); + gen_helper_cc_compute_c(reg, cpu_cc_dst, cpu_cc_src, cpu_cc_op); return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, .mask = -1, .no_setcond = true }; } |