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authorSergey Fedorov <serge.fdrv@gmail.com>2015-04-26 16:49:26 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-04-26 16:49:26 +0100
commit3d5c84ff21a8a7a3bfb3a75154be8905e62f51db (patch)
tree51f003337ad09af5e2fca875d7e3bae494056c1c /target-arm
parent7ebd5f2e03a00889619bb97e83062d27066d4a26 (diff)
downloadhqemu-3d5c84ff21a8a7a3bfb3a75154be8905e62f51db.zip
hqemu-3d5c84ff21a8a7a3bfb3a75154be8905e62f51db.tar.gz
target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1429669112-29835-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/cpu.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 3b5a93d..3ca3fa8 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -524,9 +524,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
unset_feature(env, ARM_FEATURE_EL3);
/* Disable the security extension feature bits in the processor feature
- * register as well. This is id_pfr1[7:4].
+ * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
*/
cpu->id_pfr1 &= ~0xf0;
+ cpu->id_aa64pfr0 &= ~0xf000;
}
register_cp_regs_for_features(cpu);
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