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| author | Peter Maydell <peter.maydell@linaro.org> | 2012-03-14 12:26:10 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-03-15 17:00:52 +0000 |
| commit | c98d174c24b915e9908785feb63eb3b5abe33818 (patch) | |
| tree | d0630eec1485a82d7c841dc65765ffde948fae11 /target-arm/translate.c | |
| parent | 4de47793d49e70ee048e15889d4bf139e7b36ce7 (diff) | |
| download | hqemu-c98d174c24b915e9908785feb63eb3b5abe33818.zip hqemu-c98d174c24b915e9908785feb63eb3b5abe33818.tar.gz | |
target-arm: Clear IT bits when taking exceptions in v7M
When taking an exception for an M profile core, we must clear
the IT bits. Since the IT bits are cached in env->condexec_bits
we must clear them there: writing the bits in env->uncached_cpsr
has no effect. (Reported as LP:944645.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.c')
0 files changed, 0 insertions, 0 deletions
