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authorPeter Maydell <peter.maydell@linaro.org>2011-10-19 16:14:06 +0000
committerPeter Maydell <peter.maydell@linaro.org>2011-10-19 16:14:06 +0000
commitb8b8ea05c4008343afcedf99b9c91fd750ea90e5 (patch)
tree4d1c4eee3a5e8ada8af69de5b4bafde58f80732e /target-arm/translate.c
parent477899908fd2e6ed72faf18ef5ab09f2ae746a8a (diff)
downloadhqemu-b8b8ea05c4008343afcedf99b9c91fd750ea90e5.zip
hqemu-b8b8ea05c4008343afcedf99b9c91fd750ea90e5.tar.gz
target-arm: Add ARM UDIV/SDIV support
Add support for UDIV and SDIV in ARM mode. This is a new optional feature for A profile cores (Thumb mode has had UDIV and SDIV for M profile cores for some time). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index deb0bcf..812a9e7 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7639,6 +7639,25 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
store_reg(s, rn, tmp);
}
break;
+ case 1:
+ case 3:
+ /* SDIV, UDIV */
+ if (!arm_feature(env, ARM_FEATURE_ARM_DIV)) {
+ goto illegal_op;
+ }
+ if (((insn >> 5) & 7) || (rd != 15)) {
+ goto illegal_op;
+ }
+ tmp = load_reg(s, rm);
+ tmp2 = load_reg(s, rs);
+ if (insn & (1 << 21)) {
+ gen_helper_udiv(tmp, tmp, tmp2);
+ } else {
+ gen_helper_sdiv(tmp, tmp, tmp2);
+ }
+ tcg_temp_free_i32(tmp2);
+ store_reg(s, rn, tmp);
+ break;
default:
goto illegal_op;
}
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