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author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-15 19:18:39 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:03 +0100 |
commit | 8c6afa6ab158467d1938cc92022135bc7a872006 (patch) | |
tree | 828b37b0fba9f42d50862e612e65350d32b6170c /target-arm/internals.h | |
parent | 00892383c9f5f663230921c6cf6b6d3a8a61b45b (diff) | |
download | hqemu-8c6afa6ab158467d1938cc92022135bc7a872006.zip hqemu-8c6afa6ab158467d1938cc92022135bc7a872006.tar.gz |
target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
For the A64 instruction set, the only FP/Neon disable trap
is the CPACR FPEN bits, which may indicate "enabled", "disabled"
or "disabled for EL0". Add a bit to the AArch64 tb flags indicating
whether FP/Neon access is currently enabled and make the decoder
emit code to raise exceptions on use of FP/Neon insns if it is not.
We use a new flag in DisasContext rather than borrowing the
existing vfp_enabled flag because the A32/T32 decoder is going
to need both.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
I'm aware this is a rather hard to review patch; sorry.
I have done an exhaustive check that we have fp access checks
in all code paths with the aid of the assertions added in the
next patch plus the code-coverage hack patch I posted to the
list earlier.
This patch is correct as of
09e037354 target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)
which was the last of the Neon insns to be added, so assuming
no refactoring of the code it should be fine.
Diffstat (limited to 'target-arm/internals.h')
-rw-r--r-- | target-arm/internals.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-arm/internals.h b/target-arm/internals.h index fad203b..a527f02 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -188,6 +188,13 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; } +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb) +{ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_thumb ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20); +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) |