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author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2015-06-19 14:17:44 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2015-06-19 14:17:44 +0100 |
commit | 6cb0b013a1fa421cdfb83257cd33f855cc90649a (patch) | |
tree | d7c505b89b116dd870147145cb094d4848d4c213 /target-arm/cpu.c | |
parent | 3281af8114c6b8ead02f08b58e3c36895c1ea047 (diff) | |
download | hqemu-6cb0b013a1fa421cdfb83257cd33f855cc90649a.zip hqemu-6cb0b013a1fa421cdfb83257cd33f855cc90649a.tar.gz |
target-arm: Add registers for PMSAv7
Define the arm CP registers for PMSAv7 and their accessor functions.
RGNR serves as a shared index that indexes into arrays storing the
DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd
separately from the CP interface using a new PMSA specific VMSD
subsection.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 172cf135fbd8f5cea413c00e71cc1c3cac704744.1434501320.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.c')
-rw-r--r-- | target-arm/cpu.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index a04d5c3..eb10f59 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -596,6 +596,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32 "\n", nr); return; } + + if (nr) { + env->pmsav7.drbar = g_new0(uint32_t, nr); + env->pmsav7.drsr = g_new0(uint32_t, nr); + env->pmsav7.dracr = g_new0(uint32_t, nr); + } } register_cp_regs_for_features(cpu); |