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author | Peter Crosthwaite <crosthwaitepeter@gmail.com> | 2015-06-23 20:57:35 -0700 |
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committer | Andreas Färber <afaerber@suse.de> | 2015-07-09 15:20:41 +0200 |
commit | 484406200e51eac023b346fdf987f86af1f6fe75 (patch) | |
tree | 13d4d03ac291067f3e688c9352736f5692f76391 /target-arm/cpu.c | |
parent | fb200d5f003118f63205f34bbe553efcf3a66a81 (diff) | |
download | hqemu-484406200e51eac023b346fdf987f86af1f6fe75.zip hqemu-484406200e51eac023b346fdf987f86af1f6fe75.tar.gz |
disas: arm: QOMify target specific disas setup
Move the target_disas() ARM specifics to the QOM disas_set_info hook
and delete the ARM specific code in disas.c.
This has the extra advantage of the more fully featured target_disas()
implementation now applying to monitor_disas().
Currently, target_disas() has multi-endian, thumb and AArch64
support whereas the existing monitor_disas() support only has vanilla
AA32 support.
E.G. Running an AA64 linux kernel the following -d in_asm disas happens
(taget_disas()):
IN:
0x0000000040000000: 580000c0 ldr x0, pc+24 (addr 0x40000018)
0x0000000040000004: aa1f03e1 mov x1, xzr
However before this patch, disasing the same from the monitor:
(qemu) xp/i 0x40000000
0x0000000040000000: 580000c0 stmdapl r0, {r6, r7}
After this patch:
(qemu) xp/i 0x40000000
0x0000000040000000: 580000c0 ldr x0, pc+24 (addr 0x40000018)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-arm/cpu.c')
-rw-r--r-- | target-arm/cpu.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 5a8cdb5..8b4323d 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -382,6 +382,39 @@ static inline void unset_feature(CPUARMState *env, int feature) env->features &= ~(1ULL << feature); } +static int +print_insn_thumb1(bfd_vma pc, disassemble_info *info) +{ + return print_insn_arm(pc | 1, info); +} + +static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + ARMCPU *ac = ARM_CPU(cpu); + CPUARMState *env = &ac->env; + + if (is_a64(env)) { + /* We might not be compiled with the A64 disassembler + * because it needs a C++ compiler. Leave print_insn + * unset in this case to use the caller default behaviour. + */ +#if defined(CONFIG_ARM_A64_DIS) + info->print_insn = print_insn_arm_a64; +#endif + } else if (env->thumb) { + info->print_insn = print_insn_thumb1; + } else { + info->print_insn = print_insn_arm; + } + if (env->bswap_code) { +#ifdef TARGET_WORDS_BIGENDIAN + info->endian = BFD_ENDIAN_LITTLE; +#else + info->endian = BFD_ENDIAN_BIG; +#endif + } +} + #define ARM_CPUS_PER_CLUSTER 8 static void arm_cpu_initfn(Object *obj) @@ -1368,6 +1401,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_core_xml_file = "arm-core.xml"; cc->gdb_stop_before_watchpoint = true; cc->debug_excp_handler = arm_debug_excp_handler; + + cc->disas_set_info = arm_disas_set_info; } static void cpu_register(const ARMCPUInfo *info) |