diff options
| author | Timothy Pearson <tpearson@raptorengineering.com> | 2019-05-11 15:12:49 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineering.com> | 2019-05-11 15:12:49 -0500 |
| commit | 9e80202352dd49bdd9e67b8b906d86f058431505 (patch) | |
| tree | 5673c17aad6e3833da8c4ff21b5a11f666ec9fbe /src/roms/u-boot/board/cogent/serial.h | |
| download | hqemu-master.zip hqemu-master.tar.gz | |
Diffstat (limited to 'src/roms/u-boot/board/cogent/serial.h')
| -rw-r--r-- | src/roms/u-boot/board/cogent/serial.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/roms/u-boot/board/cogent/serial.h b/src/roms/u-boot/board/cogent/serial.h new file mode 100644 index 0000000..89962d8 --- /dev/null +++ b/src/roms/u-boot/board/cogent/serial.h @@ -0,0 +1,15 @@ +/* Line Status Register bits */ +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +#define CLKRATE 3686400 /* cogent motherboard serial clk = 3.6864MHz */ +#define DEFDIV 1 /* default to 230400 bps */ + +#define br_to_div(br) (CLKRATE / (16 * (br))) +#define div_to_br(div) (CLKRATE / (16 * (div))) |
