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authorTimothy Pearson <tpearson@raptorengineering.com>2019-11-29 19:00:14 -0600
committerTimothy Pearson <tpearson@raptorengineering.com>2019-11-29 19:02:28 -0600
commit4b3250c5073149c59c5c11e06c2c0d93b6a9f5ff (patch)
treedce73321255f834f7b2d4c16fa49760edb534f27 /llvm/include/pmu/x86
parenta58047f7fbb055677e45c9a7d65ba40fbfad4b92 (diff)
downloadhqemu-2.5.1_overlay.zip
hqemu-2.5.1_overlay.tar.gz
Initial overlay of HQEMU 2.5.2 changes onto underlying 2.5.1 QEMU GIT tree2.5.1_overlay
Diffstat (limited to 'llvm/include/pmu/x86')
-rw-r--r--llvm/include/pmu/x86/x86-events.h38
1 files changed, 38 insertions, 0 deletions
diff --git a/llvm/include/pmu/x86/x86-events.h b/llvm/include/pmu/x86/x86-events.h
new file mode 100644
index 0000000..c6fdb95
--- /dev/null
+++ b/llvm/include/pmu/x86/x86-events.h
@@ -0,0 +1,38 @@
+/*
+ * (C) 2018 by Computer System Laboratory, IIS, Academia Sinica, Taiwan.
+ * See COPYRIGHT in top-level directory.
+ */
+
+#ifndef __X86_EVENTS_H
+#define __X86_EVENTS_H
+
+#include <vector>
+#include "pmu/pmu.h"
+
+namespace pmu {
+
+class PMUEvent;
+
+#if defined(__i386__)
+/*
+ * Some non-Intel clones support out of order store. wmb() ceases to be a
+ * nop for these.
+ */
+#define pmu_mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
+#define pmu_rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
+#define pmu_wmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
+#elif defined(__x86_64__)
+#define pmu_mb() asm volatile("mfence" ::: "memory")
+#define pmu_rmb() asm volatile("lfence" ::: "memory")
+#define pmu_wmb() asm volatile("sfence" ::: "memory")
+#endif
+
+int X86Init(void);
+
+} /* namespace pmu */
+
+#endif /* __X86_EVENTS_H */
+
+/*
+ * vim: ts=8 sts=4 sw=4 expandtab
+ */
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