diff options
author | Anthony Liguori <aliguori@us.ibm.com> | 2011-09-20 15:22:10 -0500 |
---|---|---|
committer | Anthony Liguori <aliguori@us.ibm.com> | 2011-09-20 15:22:10 -0500 |
commit | 03c39eb558472ab3b13a39e9159b2e1ffa6c3a43 (patch) | |
tree | f19079357c2c346d0b00a94d7ac8d85185fbdbff /hw | |
parent | c8af89af96dac46922f6664cf0ca238a6b1adf0d (diff) | |
parent | 336411cafd385be1fc3de4472595d409ac7fe2b2 (diff) | |
download | hqemu-03c39eb558472ab3b13a39e9159b2e1ffa6c3a43.zip hqemu-03c39eb558472ab3b13a39e9159b2e1ffa6c3a43.tar.gz |
Merge remote-tracking branch 'mst-tmp/for_anthony' into staging
Diffstat (limited to 'hw')
-rw-r--r-- | hw/ac97.c | 1 | ||||
-rw-r--r-- | hw/e1000.c | 3 | ||||
-rw-r--r-- | hw/es1370.c | 1 | ||||
-rw-r--r-- | hw/lsi53c895a.c | 3 | ||||
-rw-r--r-- | hw/ne2000.c | 3 | ||||
-rw-r--r-- | hw/pci.c | 76 | ||||
-rw-r--r-- | hw/pci.h | 4 | ||||
-rw-r--r-- | hw/pci_bridge.c | 85 | ||||
-rw-r--r-- | hw/pci_internals.h | 19 | ||||
-rw-r--r-- | hw/pcnet-pci.c | 2 | ||||
-rw-r--r-- | hw/rtl8139.c | 2 | ||||
-rw-r--r-- | hw/usb-ehci.c | 2 | ||||
-rw-r--r-- | hw/usb-ohci.c | 3 | ||||
-rw-r--r-- | hw/usb-uhci.c | 2 |
14 files changed, 110 insertions, 96 deletions
@@ -1311,7 +1311,6 @@ static int ac97_initfn (PCIDevice *dev) c[PCI_SUBSYSTEM_ID + 1] = 0x00; c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */ - /* TODO: RST# value should be 0. */ c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */ memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024); @@ -1156,8 +1156,7 @@ static int pci_e1000_init(PCIDevice *pci_dev) /* TODO: RST# value should be 0, PCI spec 6.2.4 */ pci_conf[PCI_CACHE_LINE_SIZE] = 0x10; - /* TODO: RST# value should be 0 if programmable, PCI spec 6.2.4 */ - pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0 + pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ e1000_mmio_setup(d); diff --git a/hw/es1370.c b/hw/es1370.c index a9387d1..2daadde 100644 --- a/hw/es1370.c +++ b/hw/es1370.c @@ -1003,7 +1003,6 @@ static int es1370_initfn (PCIDevice *dev) c[0xdc] = 0x00; #endif - /* TODO: RST# value should be 0. */ c[PCI_INTERRUPT_PIN] = 1; c[PCI_MIN_GNT] = 0x0c; c[PCI_MAX_LAT] = 0x80; diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c index dbb3bdf..75a03a7 100644 --- a/hw/lsi53c895a.c +++ b/hw/lsi53c895a.c @@ -2106,8 +2106,7 @@ static int lsi_scsi_init(PCIDevice *dev) /* PCI latency timer = 255 */ pci_conf[PCI_LATENCY_TIMER] = 0xff; - /* TODO: RST# value should be 0 */ - /* Interrupt pin 1 */ + /* Interrupt pin A */ pci_conf[PCI_INTERRUPT_PIN] = 0x01; memory_region_init_io(&s->mmio_io, &lsi_mmio_ops, s, "lsi-mmio", 0x400); diff --git a/hw/ne2000.c b/hw/ne2000.c index a035a85..62e082f 100644 --- a/hw/ne2000.c +++ b/hw/ne2000.c @@ -749,8 +749,7 @@ static int pci_ne2000_init(PCIDevice *pci_dev) uint8_t *pci_conf; pci_conf = d->dev.config; - /* TODO: RST# value should be 0. PCI spec 6.2.4 */ - pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0 + pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ s = &d->ne2000; ne2000_setup_io(s, 0x100); @@ -878,7 +878,6 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, r = &pci_dev->io_regions[region_num]; r->addr = PCI_BAR_UNMAPPED; r->size = size; - r->filtered_size = size; r->type = type; r->memory = NULL; @@ -909,41 +908,6 @@ pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) return pci_dev->io_regions[region_num].addr; } -static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size, - uint8_t type) -{ - pcibus_t base = *addr; - pcibus_t limit = *addr + *size - 1; - PCIDevice *br; - - for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) { - uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); - - if (type & PCI_BASE_ADDRESS_SPACE_IO) { - if (!(cmd & PCI_COMMAND_IO)) { - goto no_map; - } - } else { - if (!(cmd & PCI_COMMAND_MEMORY)) { - goto no_map; - } - } - - base = MAX(base, pci_bridge_get_base(br, type)); - limit = MIN(limit, pci_bridge_get_limit(br, type)); - } - - if (base > limit) { - goto no_map; - } - *addr = base; - *size = limit - base + 1; - return; -no_map: - *addr = PCI_BAR_UNMAPPED; - *size = 0; -} - static pcibus_t pci_bar_address(PCIDevice *d, int reg, uint8_t type, pcibus_t size) { @@ -1013,7 +977,7 @@ static void pci_update_mappings(PCIDevice *d) { PCIIORegion *r; int i; - pcibus_t new_addr, filtered_size; + pcibus_t new_addr; for(i = 0; i < PCI_NUM_REGIONS; i++) { r = &d->io_regions[i]; @@ -1024,14 +988,8 @@ static void pci_update_mappings(PCIDevice *d) new_addr = pci_bar_address(d, i, r->type, r->size); - /* bridge filtering */ - filtered_size = r->size; - if (new_addr != PCI_BAR_UNMAPPED) { - pci_bridge_filter(d, &new_addr, &filtered_size, r->type); - } - /* This bar isn't changed */ - if (new_addr == r->addr && filtered_size == r->filtered_size) + if (new_addr == r->addr) continue; /* now do the real mapping */ @@ -1039,15 +997,7 @@ static void pci_update_mappings(PCIDevice *d) memory_region_del_subregion(r->address_space, r->memory); } r->addr = new_addr; - r->filtered_size = filtered_size; if (r->addr != PCI_BAR_UNMAPPED) { - /* - * TODO: currently almost all the map funcions assumes - * filtered_size == size and addr & ~(size - 1) == addr. - * However with bridge filtering, they aren't always true. - * Teach them such cases, such that filtered_size < size and - * addr & (size - 1) != 0. - */ if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { memory_region_add_subregion_overlap(r->address_space, r->addr, @@ -1564,22 +1514,6 @@ PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, return res; } -static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d) -{ - pci_update_mappings(d); -} - -void pci_bridge_update_mappings(PCIBus *b) -{ - PCIBus *child; - - pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn); - - QLIST_FOREACH(child, &b->child, sibling) { - pci_bridge_update_mappings(child); - } -} - /* Whether a given bus number is in range of the secondary * bus of the given bridge device. */ static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) @@ -2016,12 +1950,6 @@ void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; } -/* Reserve space for capability at a known offset (to call after load). */ -void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size) -{ - memset(pdev->used + offset, 0xff, size); -} - uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) { return pci_find_capability_list(pdev, cap_id, NULL); @@ -90,7 +90,6 @@ typedef struct PCIIORegion { pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ #define PCI_BAR_UNMAPPED (~(pcibus_t)0) pcibus_t size; - pcibus_t filtered_size; uint8_t type; MemoryRegion *memory; MemoryRegion *address_space; @@ -209,8 +208,6 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); -void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size); - uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); @@ -275,7 +272,6 @@ int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, void do_pci_info_print(Monitor *mon, const QObject *data); void do_pci_info(Monitor *mon, QObject **ret_data); -void pci_bridge_update_mappings(PCIBus *b); void pci_device_deassert_intx(PCIDevice *dev); diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c index 464d897..b6287cd 100644 --- a/hw/pci_bridge.c +++ b/hw/pci_bridge.c @@ -135,6 +135,76 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) return limit; } +static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias, + uint8_t type, const char *name, + MemoryRegion *space, + MemoryRegion *parent_space, + bool enabled) +{ + pcibus_t base = pci_bridge_get_base(&bridge->dev, type); + pcibus_t limit = pci_bridge_get_limit(&bridge->dev, type); + /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly. + * Apparently no way to do this with existing memory APIs. */ + pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0; + + memory_region_init_alias(alias, name, space, base, size); + memory_region_add_subregion_overlap(parent_space, base, alias, 1); +} + +static void pci_bridge_cleanup_alias(MemoryRegion *alias, + MemoryRegion *parent_space) +{ + memory_region_del_subregion(parent_space, alias); + memory_region_destroy(alias); +} + +static void pci_bridge_region_init(PCIBridge *br) +{ + PCIBus *parent = br->dev.bus; + uint16_t cmd = pci_get_word(br->dev.config + PCI_COMMAND); + + pci_bridge_init_alias(br, &br->alias_pref_mem, + PCI_BASE_ADDRESS_MEM_PREFETCH, + "pci_bridge_pref_mem", + &br->address_space_mem, + parent->address_space_mem, + cmd & PCI_COMMAND_MEMORY); + pci_bridge_init_alias(br, &br->alias_mem, + PCI_BASE_ADDRESS_SPACE_MEMORY, + "pci_bridge_mem", + &br->address_space_mem, + parent->address_space_mem, + cmd & PCI_COMMAND_MEMORY); + pci_bridge_init_alias(br, &br->alias_io, + PCI_BASE_ADDRESS_SPACE_IO, + "pci_bridge_io", + &br->address_space_io, + parent->address_space_io, + cmd & PCI_COMMAND_IO); + /* TODO: optinal VGA and VGA palette snooping support. */ +} + +static void pci_bridge_region_cleanup(PCIBridge *br) +{ + PCIBus *parent = br->dev.bus; + pci_bridge_cleanup_alias(&br->alias_io, + parent->address_space_io); + pci_bridge_cleanup_alias(&br->alias_mem, + parent->address_space_mem); + pci_bridge_cleanup_alias(&br->alias_pref_mem, + parent->address_space_mem); +} + +static void pci_bridge_update_mappings(PCIBridge *br) +{ + /* Make updates atomic to: handle the case of one VCPU updating the bridge + * while another accesses an unaffected region. */ + memory_region_transaction_begin(); + pci_bridge_region_cleanup(br); + pci_bridge_region_init(br); + memory_region_transaction_commit(); +} + /* default write_config function for PCI-to-PCI bridge */ void pci_bridge_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) @@ -145,13 +215,15 @@ void pci_bridge_write_config(PCIDevice *d, pci_default_write_config(d, address, val, len); - if (/* io base/limit */ + if (ranges_overlap(address, len, PCI_COMMAND, 2) || + + /* io base/limit */ ranges_overlap(address, len, PCI_IO_BASE, 2) || /* memory base/limit, prefetchable base/limit and io base/limit upper 16 */ ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { - pci_bridge_update_mappings(&s->sec_bus); + pci_bridge_update_mappings(s); } newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); @@ -246,7 +318,11 @@ int pci_bridge_initfn(PCIDevice *dev) br->bus_name); sec_bus->parent_dev = dev; sec_bus->map_irq = br->map_irq; - + sec_bus->address_space_mem = &br->address_space_mem; + memory_region_init(&br->address_space_mem, "pci_pridge_pci", INT64_MAX); + sec_bus->address_space_io = &br->address_space_io; + memory_region_init(&br->address_space_io, "pci_bridge_io", 65536); + pci_bridge_region_init(br); QLIST_INIT(&sec_bus->child); QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling); return 0; @@ -258,6 +334,9 @@ int pci_bridge_exitfn(PCIDevice *pci_dev) PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); assert(QLIST_EMPTY(&s->sec_bus.child)); QLIST_REMOVE(&s->sec_bus, sibling); + pci_bridge_region_cleanup(s); + memory_region_destroy(&s->address_space_mem); + memory_region_destroy(&s->address_space_io); /* qbus_free() is called automatically by qdev_free() */ return 0; } diff --git a/hw/pci_internals.h b/hw/pci_internals.h index c7fd23d..96690b7 100644 --- a/hw/pci_internals.h +++ b/hw/pci_internals.h @@ -24,7 +24,6 @@ struct PCIBus { void *irq_opaque; PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX]; PCIDevice *parent_dev; - target_phys_addr_t mem_base; MemoryRegion *address_space_mem; MemoryRegion *address_space_io; @@ -42,6 +41,24 @@ struct PCIBridge { /* private member */ PCIBus sec_bus; + /* + * Memory regions for the bridge's address spaces. These regions are not + * directly added to system_memory/system_io or its descendants. + * Bridge's secondary bus points to these, so that devices + * under the bridge see these regions as its address spaces. + * The regions are as large as the entire address space - + * they don't take into account any windows. + */ + MemoryRegion address_space_mem; + MemoryRegion address_space_io; + /* + * Aliases for each of the address space windows that the bridge + * can forward. Mapped into the bridge's parent's address space, + * as subregions. + */ + MemoryRegion alias_pref_mem; + MemoryRegion alias_mem; + MemoryRegion alias_io; pci_map_irq_fn map_irq; const char *bus_name; }; diff --git a/hw/pcnet-pci.c b/hw/pcnet-pci.c index 51e1320..fb2a00c 100644 --- a/hw/pcnet-pci.c +++ b/hw/pcnet-pci.c @@ -285,7 +285,7 @@ static int pci_pcnet_init(PCIDevice *pci_dev) pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0); pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0); - pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0 + pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ pci_conf[PCI_MIN_GNT] = 0x06; pci_conf[PCI_MAX_LAT] = 0xff; diff --git a/hw/rtl8139.c b/hw/rtl8139.c index c5de5b4..3753950 100644 --- a/hw/rtl8139.c +++ b/hw/rtl8139.c @@ -3464,7 +3464,7 @@ static int pci_rtl8139_init(PCIDevice *dev) uint8_t *pci_conf; pci_conf = s->dev.config; - pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */ + pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ /* TODO: start of capability list, but no capability * list bit in status register, and offset 0xdc seems unused. */ pci_conf[PCI_CAPABILITY_LIST] = 0xdc; diff --git a/hw/usb-ehci.c b/hw/usb-ehci.c index e9e0789..27376a2 100644 --- a/hw/usb-ehci.c +++ b/hw/usb-ehci.c @@ -2291,7 +2291,7 @@ static int usb_ehci_initfn(PCIDevice *dev) pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); - pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3 + pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c index 503ca2d..c3be65a 100644 --- a/hw/usb-ohci.c +++ b/hw/usb-ohci.c @@ -1780,8 +1780,7 @@ static int usb_ohci_initfn_pci(struct PCIDevice *dev) OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev); ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */ - /* TODO: RST# value should be 0. */ - ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ + ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ if (usb_ohci_init(&ohci->state, &dev->qdev, ohci->num_ports, 0, ohci->masterbus, ohci->firstport) != 0) { diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c index 64f7b36..17992cf 100644 --- a/hw/usb-uhci.c +++ b/hw/usb-uhci.c @@ -1131,7 +1131,7 @@ static int usb_uhci_common_initfn(PCIDevice *dev) pci_conf[PCI_CLASS_PROG] = 0x00; /* TODO: reset value should be 0. */ - pci_conf[PCI_INTERRUPT_PIN] = 4; // interrupt pin 3 + pci_conf[PCI_INTERRUPT_PIN] = 4; /* interrupt pin D */ pci_conf[USB_SBRN] = USB_RELEASE_1; // release number if (s->masterbus) { |