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author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-17 17:14:51 +0000 |
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committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-17 17:14:51 +0000 |
commit | 87ecb68bdf8a3e40ef885ddbb7ca1797dca40ebf (patch) | |
tree | f8c5c8eb6e34a6d492a9638d62489e7569f8b046 /hw/sun4m.h | |
parent | 257514ddce752fe0b4aeb4b7957bc5661eadbef8 (diff) | |
download | hqemu-87ecb68bdf8a3e40ef885ddbb7ca1797dca40ebf.zip hqemu-87ecb68bdf8a3e40ef885ddbb7ca1797dca40ebf.tar.gz |
Break up vl.h.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/sun4m.h')
-rw-r--r-- | hw/sun4m.h | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/hw/sun4m.h b/hw/sun4m.h new file mode 100644 index 0000000..12fa832 --- /dev/null +++ b/hw/sun4m.h @@ -0,0 +1,73 @@ +#ifndef SUN4M_H +#define SUN4M_H + +/* Devices used by sparc32 system. */ + +/* iommu.c */ +void *iommu_init(target_phys_addr_t addr, uint32_t version); +void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, + uint8_t *buf, int len, int is_write); +static inline void sparc_iommu_memory_read(void *opaque, + target_phys_addr_t addr, + uint8_t *buf, int len) +{ + sparc_iommu_memory_rw(opaque, addr, buf, len, 0); +} + +static inline void sparc_iommu_memory_write(void *opaque, + target_phys_addr_t addr, + uint8_t *buf, int len) +{ + sparc_iommu_memory_rw(opaque, addr, buf, len, 1); +} + +/* tcx.c */ +void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base, + unsigned long vram_offset, int vram_size, int width, int height, + int depth); + +/* slavio_intctl.c */ +void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg, + const uint32_t *intbit_to_level, + qemu_irq **irq, qemu_irq **cpu_irq, + qemu_irq **parent_irq, unsigned int cputimer); +void slavio_pic_info(void *opaque); +void slavio_irq_info(void *opaque); + +/* slavio_timer.c */ +void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq, + qemu_irq *cpu_irqs); + +/* slavio_serial.c */ +SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq, + CharDriverState *chr1, CharDriverState *chr2); +void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq); + +/* slavio_misc.c */ +void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base, + qemu_irq irq); +void slavio_set_power_fail(void *opaque, int power_failing); + +/* esp.c */ +void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id); +void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr, + void *dma_opaque, qemu_irq irq, qemu_irq *reset); + +/* cs4231.c */ +void cs_init(target_phys_addr_t base, int irq, void *intctl); + +/* sparc32_dma.c */ +void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, + void *iommu, qemu_irq **dev_irq, qemu_irq **reset); +void ledma_memory_read(void *opaque, target_phys_addr_t addr, + uint8_t *buf, int len, int do_bswap); +void ledma_memory_write(void *opaque, target_phys_addr_t addr, + uint8_t *buf, int len, int do_bswap); +void espdma_memory_read(void *opaque, uint8_t *buf, int len); +void espdma_memory_write(void *opaque, uint8_t *buf, int len); + +/* pcnet.c */ +void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque, + qemu_irq irq, qemu_irq *reset); + +#endif |