diff options
author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-08 23:30:44 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-08 23:30:44 +0000 |
commit | 522777bbafd9151da17199f558c036f791b5cac1 (patch) | |
tree | 9fc73b6e621fc412fc0af75e67fd296aa4104997 /dyngen.h | |
parent | 85028e4db6b92b9b2f0282971efdb0a0144bfcd3 (diff) | |
download | hqemu-522777bbafd9151da17199f558c036f791b5cac1.zip hqemu-522777bbafd9151da17199f558c036f791b5cac1.tar.gz |
Make detection of unsupported hosts easier, inspired by a patch from
Stefan Weil.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2791 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'dyngen.h')
-rw-r--r-- | dyngen.h | 59 |
1 files changed, 17 insertions, 42 deletions
@@ -28,25 +28,11 @@ int __op_param1, __op_param2, __op_param3; #endif int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3; -#ifdef __i386__ +#if defined(__i386__) || defined(__x86_64__) || defined(__s390__) static inline void flush_icache_range(unsigned long start, unsigned long stop) { } -#endif - -#ifdef __x86_64__ -static inline void flush_icache_range(unsigned long start, unsigned long stop) -{ -} -#endif - -#ifdef __s390__ -static inline void flush_icache_range(unsigned long start, unsigned long stop) -{ -} -#endif - -#ifdef __ia64__ +#elif defined(__ia64__) static inline void flush_icache_range(unsigned long start, unsigned long stop) { while (start < stop) { @@ -55,9 +41,7 @@ static inline void flush_icache_range(unsigned long start, unsigned long stop) } asm volatile (";;sync.i;;srlz.i;;"); } -#endif - -#ifdef __powerpc__ +#elif defined(__powerpc__) #define MIN_CACHE_LINE_SIZE 8 /* conservative value */ @@ -78,17 +62,12 @@ static void inline flush_icache_range(unsigned long start, unsigned long stop) asm volatile ("sync" : : : "memory"); asm volatile ("isync" : : : "memory"); } -#endif - -#ifdef __alpha__ +#elif defined(__alpha__) static inline void flush_icache_range(unsigned long start, unsigned long stop) { asm ("imb"); } -#endif - -#ifdef __sparc__ - +#elif defined(__sparc__) static void inline flush_icache_range(unsigned long start, unsigned long stop) { unsigned long p; @@ -99,10 +78,7 @@ static void inline flush_icache_range(unsigned long start, unsigned long stop) for (; p < stop; p += 8) __asm__ __volatile__("flush\t%0" : : "r" (p)); } - -#endif - -#ifdef __arm__ +#elif defined(__arm__) static inline void flush_icache_range(unsigned long start, unsigned long stop) { register unsigned long _beg __asm ("a1") = start; @@ -110,14 +86,22 @@ static inline void flush_icache_range(unsigned long start, unsigned long stop) register unsigned long _flg __asm ("a3") = 0; __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); } -#endif +#elif defined(__mc68000) -#ifdef __mc68000 -#include <asm/cachectl.h> +# include <asm/cachectl.h> static inline void flush_icache_range(unsigned long start, unsigned long stop) { cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16); } +#elif defined(__mips__) + +#include <sys/cachectl.h> +static inline void flush_icache_range(unsigned long start, unsigned long stop) +{ + _flush_cache ((void *)start, stop - start, BCACHE); +} +#else +#error unsupported CPU #endif #ifdef __alpha__ @@ -248,7 +232,6 @@ static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr, #ifdef __ia64 - /* Patch instruction with "val" where "mask" has 1 bits. */ static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val) { @@ -463,11 +446,3 @@ static inline void ia64_apply_fixes (uint8_t **gen_code_pp, } #endif - -#ifdef __mips__ -#include <sys/cachectl.h> -static inline void flush_icache_range(unsigned long start, unsigned long stop) -{ - _flush_cache ((void *)start, stop - start, BCACHE); -} -#endif |