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author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2003-06-15 19:45:20 +0000 |
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committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2003-06-15 19:45:20 +0000 |
commit | 03daf0e361d58eb5a6d8ea9963ca63f919c15f85 (patch) | |
tree | f3b7d3fabf2f69e4c21c7194383f2c7ca73afedf /dyngen.h | |
parent | d219f7e7edf7874ae1572d9c6a8e9283c6f36bbc (diff) | |
download | hqemu-03daf0e361d58eb5a6d8ea9963ca63f919c15f85.zip hqemu-03daf0e361d58eb5a6d8ea9963ca63f919c15f85.tar.gz |
moved cache flush to dyngen header
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@235 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'dyngen.h')
-rw-r--r-- | dyngen.h | 76 |
1 files changed, 76 insertions, 0 deletions
@@ -18,6 +18,82 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +int __op_param1, __op_param2, __op_param3; +int __op_jmp0, __op_jmp1; + +#ifdef __i386__ +static inline void flush_icache_range(unsigned long start, unsigned long stop) +{ +} +#endif + +#ifdef __s390__ +static inline void flush_icache_range(unsigned long start, unsigned long stop) +{ +} +#endif + +#ifdef __ia64__ +static inline void flush_icache_range(unsigned long start, unsigned long stop) +{ +} +#endif + +#ifdef __powerpc__ + +#define MIN_CACHE_LINE_SIZE 8 /* conservative value */ + +static void inline flush_icache_range(unsigned long start, unsigned long stop) +{ + unsigned long p; + + p = start & ~(MIN_CACHE_LINE_SIZE - 1); + stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1); + + for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) { + asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); + } + asm volatile ("sync" : : : "memory"); + for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) { + asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); + } + asm volatile ("sync" : : : "memory"); + asm volatile ("isync" : : : "memory"); +} +#endif + +#ifdef __alpha__ +static inline void flush_icache_range(unsigned long start, unsigned long stop) +{ + asm ("imb"); +} +#endif + +#ifdef __sparc__ + +static void inline flush_icache_range(unsigned long start, unsigned long stop) +{ + unsigned long p; + + p = start & ~(8UL - 1UL); + stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL); + + for (; p < stop; p += 8) + __asm__ __volatile__("flush\t%0" : : "r" (p)); +} + +#endif + +#ifdef __arm__ +static inline void flush_icache_range(unsigned long start, unsigned long stop) +{ + register unsigned long _beg __asm ("a1") = start; + register unsigned long _end __asm ("a2") = stop; + register unsigned long _flg __asm ("a3") = 0; + __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); +} +#endif + #ifdef __alpha__ register int gp asm("$29"); |