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| author | Peter Crosthwaite <crosthwaitepeter@gmail.com> | 2015-11-10 13:37:33 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-11-10 13:37:33 +0000 |
| commit | 40340e5f221935723bffbca305f3090e8866c818 (patch) | |
| tree | 7741e0ce45fdf9843df4b31423e016077a7e34a3 /MAINTAINERS | |
| parent | dca6eeed8c2a1c131d161139428dd18a35e58b03 (diff) | |
| download | hqemu-40340e5f221935723bffbca305f3090e8866c818.zip hqemu-40340e5f221935723bffbca305f3090e8866c818.tar.gz | |
arm: highbank: Implement PSCI and dummy monitor
Firstly, enable monitor mode and PSCI, both of which are features of
this board.
In addition to PSCI, this board also uses SMC for cache maintenance
ops. This means we need a secure monitor to catch these and nop them.
Use the ARM boot board-setup feature to implement this. The SMC trap
implements the needed nop while all other traps will pen the CPU.
As a KVM CPU cannot run in secure mode, do not do the board-setup if
not running TCG. Report a warning explaining the limitation in this
case.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 0fd0d12f0fa666c86616c89447861a70dbe27312.1447007690.git.crosthwaite.peter@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions
