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author | Richard Henderson <rth@twiddle.net> | 2015-12-11 09:17:45 -0800 |
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committer | Timothy Pearson <tpearson@raptorengineering.com> | 2019-11-29 19:32:25 -0600 |
commit | 6b8b5330fe1d83d26b05388cdbada83270f21fd5 (patch) | |
tree | 3d3027080f8b941009bf972c7d151632740efb7d | |
parent | 6e73317d5709765b57771345c37fc4da1618f502 (diff) | |
download | hqemu-6b8b5330fe1d83d26b05388cdbada83270f21fd5.zip hqemu-6b8b5330fe1d83d26b05388cdbada83270f21fd5.tar.gz |
tcg: Remove lingering references to gen_opc_buf
Three in comments and one in code in the stub tcg_liveness_analysis.
Signed-off-by: Richard Henderson <rth@twiddle.net>
-rw-r--r-- | target-arm/translate.c | 3 | ||||
-rw-r--r-- | target-i386/translate.c | 3 | ||||
-rw-r--r-- | target-unicore32/translate.c | 3 | ||||
-rw-r--r-- | tcg/tcg.c | 3 |
4 files changed, 4 insertions, 8 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index c8b071c..2b2728f 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11480,8 +11480,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) return false; } -/* generate intermediate code in gen_opc_buf and gen_opparam_buf for - basic block 'tb'. */ +/* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) { ARMCPU *cpu = arm_env_get_cpu(env); diff --git a/target-i386/translate.c b/target-i386/translate.c index 624c9da..de71dba 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -8394,8 +8394,7 @@ void tcg_x86_init(void) copy_tcg_context_global(); } -/* generate intermediate code in gen_opc_buf and gen_opparam_buf for - basic block 'tb'. */ +/* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) { X86CPU *cpu = x86_env_get_cpu(env); diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 7dbfe3b..ec2cc13 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1860,8 +1860,7 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s) } } -/* generate intermediate code in gen_opc_buf and gen_opparam_buf for - basic block 'tb'. */ +/* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb) { UniCore32CPU *cpu = uc32_env_get_cpu(env); @@ -1775,8 +1775,7 @@ void tcg_liveness_analysis(TCGContext *s) /* dummy liveness analysis */ void tcg_liveness_analysis(TCGContext *s) { - int nb_ops; - nb_ops = s->gen_opc_ptr - s->gen_opc_buf; + int nb_ops = s->gen_next_op_idx; s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t)); memset(s->op_dead_args, 0, nb_ops * sizeof(uint16_t)); |