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author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-03 17:57:36 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-03 17:57:36 +0000 |
commit | 551bd27f22638c854c43d7e6417d549764311c31 (patch) | |
tree | b67965e4923a4b5367c47686b279be46ba79c2a0 | |
parent | 06e80fc92715ca720d23526f6d3db8c78fd8971c (diff) | |
download | hqemu-551bd27f22638c854c43d7e6417d549764311c31.zip hqemu-551bd27f22638c854c43d7e6417d549764311c31.tar.gz |
Convert remaining __builtin_expect to likely/unlikely, by Jan Kiszka.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4840 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r-- | cpu-exec.c | 6 | ||||
-rw-r--r-- | exec-all.h | 4 | ||||
-rw-r--r-- | softmmu_header.h | 12 | ||||
-rw-r--r-- | target-arm/op_helper.c | 2 | ||||
-rw-r--r-- | target-arm/translate.c | 4 | ||||
-rw-r--r-- | target-cris/op_helper.c | 2 | ||||
-rw-r--r-- | target-cris/translate.c | 2 | ||||
-rw-r--r-- | target-m68k/op_helper.c | 2 | ||||
-rw-r--r-- | target-m68k/translate.c | 4 |
9 files changed, 19 insertions, 19 deletions
@@ -224,8 +224,8 @@ static inline TranslationBlock *tb_find_fast(void) #error unsupported CPU #endif tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; - if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base || - tb->flags != flags, 0)) { + if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || + tb->flags != flags)) { tb = tb_find_slow(pc, cs_base, flags); } return tb; @@ -360,7 +360,7 @@ int cpu_exec(CPUState *env1) next_tb = 0; /* force lookup of first TB */ for(;;) { interrupt_request = env->interrupt_request; - if (__builtin_expect(interrupt_request, 0) && + if (unlikely(interrupt_request) && likely(!(env->singlestep_enabled & SSTEP_NOIRQ))) { if (interrupt_request & CPU_INTERRUPT_DEBUG) { env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; @@ -357,8 +357,8 @@ static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx = cpu_mmu_index(env1); - if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code != - (addr & TARGET_PAGE_MASK), 0)) { + if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code != + (addr & TARGET_PAGE_MASK))) { ldub_code(addr); } pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; diff --git a/softmmu_header.h b/softmmu_header.h index 481051e..512e5a2 100644 --- a/softmmu_header.h +++ b/softmmu_header.h @@ -231,8 +231,8 @@ static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr) addr = ptr; page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx = CPU_MMU_INDEX; - if (__builtin_expect(env->tlb_table[mmu_idx][page_index].ADDR_READ != - (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) { + if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ != + (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx); } else { physaddr = addr + env->tlb_table[mmu_idx][page_index].addend; @@ -252,8 +252,8 @@ static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr) addr = ptr; page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx = CPU_MMU_INDEX; - if (__builtin_expect(env->tlb_table[mmu_idx][page_index].ADDR_READ != - (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) { + if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ != + (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx); } else { physaddr = addr + env->tlb_table[mmu_idx][page_index].addend; @@ -277,8 +277,8 @@ static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE addr = ptr; page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx = CPU_MMU_INDEX; - if (__builtin_expect(env->tlb_table[mmu_idx][page_index].addr_write != - (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) { + if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write != + (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx); } else { physaddr = addr + env->tlb_table[mmu_idx][page_index].addend; diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 5d9fd84..5b5581f 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -97,7 +97,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) saved_env = env; env = cpu_single_env; ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); - if (__builtin_expect(ret, 0)) { + if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ pc = (unsigned long)retaddr; diff --git a/target-arm/translate.c b/target-arm/translate.c index e03de44..a3aabd2 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3393,7 +3393,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest) static inline void gen_jmp (DisasContext *s, uint32_t dest) { - if (__builtin_expect(s->singlestep_enabled, 0)) { + if (unlikely(s->singlestep_enabled)) { /* An indirect jump so that we still trigger the debug exception. */ if (s->thumb) dest |= 1; @@ -8703,7 +8703,7 @@ static inline int gen_intermediate_code_internal(CPUState *env, /* At this stage dc->condjmp will only be set when the skipped instruction was a conditional branch or trap, and the PC has already been written. */ - if (__builtin_expect(env->singlestep_enabled, 0)) { + if (unlikely(env->singlestep_enabled)) { /* Make sure the pc is updated, and raise a debug exception. */ if (dc->condjmp) { gen_set_condexec(dc); diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index 148c1e0..fcf8070 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -61,7 +61,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) D(fprintf(logfile, "%s pc=%x tpc=%x ra=%x\n", __func__, env->pc, env->debug1, retaddr)); ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); - if (__builtin_expect(ret, 0)) { + if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ pc = (unsigned long)retaddr; diff --git a/target-cris/translate.c b/target-cris/translate.c index 81b6132..d971d1d 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3191,7 +3191,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, cris_evaluate_flags (dc); - if (__builtin_expect(env->singlestep_enabled, 0)) { + if (unlikely(env->singlestep_enabled)) { tcg_gen_movi_tl(env_pc, npc); t_gen_raise_exception(EXCP_DEBUG); } else { diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index f2e9f03..aa36a33 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -61,7 +61,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) saved_env = env; env = cpu_single_env; ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); - if (__builtin_expect(ret, 0)) { + if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ pc = (unsigned long)retaddr; diff --git a/target-m68k/translate.c b/target-m68k/translate.c index e808db5..9486c31 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -873,7 +873,7 @@ static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) TranslationBlock *tb; tb = s->tb; - if (__builtin_expect (s->singlestep_enabled, 0)) { + if (unlikely(s->singlestep_enabled)) { gen_exception(s, dest, EXCP_DEBUG); } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || (s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { @@ -2991,7 +2991,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, if (tb->cflags & CF_LAST_IO) gen_io_end(); - if (__builtin_expect(env->singlestep_enabled, 0)) { + if (unlikely(env->singlestep_enabled)) { /* Make sure the pc is updated, and raise a debug exception. */ if (!dc->is_jmp) { gen_flush_cc_op(dc); |