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author | Paolo Bonzini <pbonzini@redhat.com> | 2014-11-11 13:14:18 +0100 |
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committer | Paolo Bonzini <pbonzini@redhat.com> | 2014-11-24 14:37:45 +0100 |
commit | 5224c88dd3f771702d450780a25f155e0fc8bb2b (patch) | |
tree | 1b0c5806fb6599f184a861598ed057481ee1300f | |
parent | 8092cb71322ca488deeb7c750ff8022ffcc2f9a6 (diff) | |
download | hqemu-5224c88dd3f771702d450780a25f155e0fc8bb2b.zip hqemu-5224c88dd3f771702d450780a25f155e0fc8bb2b.tar.gz |
apic: fix incorrect handling of ExtINT interrupts wrt processor priority
This fixes another failure with ExtINT, demonstrated by QNX. The failure
mode is as follows:
- IPI sent to cpu 0 (bit set in APIC irr)
- IPI accepted by cpu 0 (bit cleared in irr, set in isr)
- IPI sent to cpu 0 (bit set in both irr and isr)
- PIC interrupt sent to cpu 0
The PIC interrupt causes CPU_INTERRUPT_HARD to be set, but
apic_irq_pending observes that the highest pending APIC interrupt priority
(the IPI) is the same as the processor priority (since the IPI is still
being handled), so apic_get_interrupt returns a spurious interrupt rather
than the pending PIC interrupt. The result is an endless sequence of
spurious interrupts, since nothing will clear CPU_INTERRUPT_HARD.
Instead, ExtINT interrupts should have ignored the processor priority.
Calling apic_check_pic early in apic_get_interrupt ensures that
apic_deliver_pic_intr is called instead of delivering the spurious
interrupt. apic_deliver_pic_intr then clears CPU_INTERRUPT_HARD if needed.
Reported-by: Richard Bilson <rbilson@qnx.com>
Tested-by: Richard Bilson <rbilson@qnx.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
-rw-r--r-- | hw/intc/apic.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 6ec5861..0f97b47 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -571,7 +571,10 @@ int apic_get_interrupt(DeviceState *dev) apic_sync_vapic(s, SYNC_FROM_VAPIC); intno = apic_irq_pending(s); - if (intno == 0) { + /* if there is an interrupt from the 8259, let the caller handle + * that first since ExtINT interrupts ignore the priority. + */ + if (intno == 0 || apic_check_pic(s)) { apic_sync_vapic(s, SYNC_TO_VAPIC); return -1; } else if (intno < 0) { @@ -582,9 +585,6 @@ int apic_get_interrupt(DeviceState *dev) apic_set_bit(s->isr, intno); apic_sync_vapic(s, SYNC_TO_VAPIC); - /* re-inject if there is still a pending PIC interrupt */ - apic_check_pic(s); - apic_update_irq(s); return intno; |