| Commit message (Collapse) | Author | Age | Files | Lines |
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list, flashrom will claim that no chip is there
Handle these cases gracefully. flashrom will ignore generic matches if a
specific chip was found, so this will have no impact on supported chips,
but help a lot for a first quick analysis by the user or developer. The only
drawback is that unknown chips may be recognized multiple times until they
are added to flashchips.[ch].
Corresponding to flashrom svn r767.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marcj303@gmail.com>
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correct range, essentially rendering the functionality useless
This patch simplifies the code and fixes the bug. Thanks to Luke Dashjr
for testing. Mark Winbond W29C040P as supported.
Corresponding to flashrom svn r757.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luke Dashjr <luke_coreboot@dashjr.org>
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Corresponding to flashrom svn r756.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Cosmetics: Place curly brackets on a common line. Add MX25V512 as alias
name to MX25L512. Add MX25V8005 as alias name to MX25L8005. Add erase block
definitions for MX25L2005, MX25L4005, MX25L8005, MX25L1605 and change their
status to TEST_OK_PRW where applicable.
Corresponding to flashrom svn r738.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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See http://www.coreboot.org/pipermail/coreboot/2009-July/050675.html.
Corresponding to flashrom svn r733.
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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(unsupported) chip erase
Annotate SST49LF004B quirks for TBL#. Add TEST_OK_PRW which is useful when a
PREW chip gets a new erase routine. Change a few erase function prototypes
to use unsigned int instead of int.
Corresponding to flashrom svn r731.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
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I tested it on the Wyse Winterm S50 see attached test results.
Corresponding to flashrom svn r730.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Corresponding to flashrom svn r721.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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functions in struct flashchip
I decided to fill in the info for a few chips to illustrate how this works
both for uniform and non-uniform sector sizes. struct eraseblock{ int size;
/* Eraseblock size */ int count; /* Number of contiguous blocks with that
size */ }; struct eraseblock doesn't correspond with a single erase block,
but with a group of contiguous erase blocks having the same size. Given a
(top boot block) flash chip with the following weird, but real-life structure:
top 16384 8192 8192 32768 65536 65536 65536 65536 65536 65536 65536 bottom we
get the following encoding: {65536,7},{32768,1},{8192,2},{16384,1} Although
the number of blocks is bigger than 4, the number of block groups is only 4.
If you ever add some flash chips with more than 4 contiguous block groups,
the definition will not fit into the 4-member array anymore and gcc will
recognize that and error out. No undetected overflow possible. In that case,
you simply increase array size a bit. For modern flash chips with uniform
erase block size, you only need one array member anyway. Of course data types
will need to be changed if you ever get flash chips with more than 2^30
erase blocks, but even with the lowest known erase granularity of 256 bytes,
these flash chips will have to have a size of a quarter Terabyte. I'm pretty
confident we won't see such big EEPROMs in the near future (or at least not
attached in a way that makes flashrom usable). For SPI chips, we even have
a guaranteed safety factor of 4096 over the maximum SPI chip size (which is
2^24). And if such a big flash chip has uniform erase block size, you could
even split it among the 4 array members. If you change int count to unsigned
int count, the storable size doubles. So with a split and a slight change
of data type, the maximum ROM chip size is 2 Terabytes. Since many chips
have multiple block erase functions where the eraseblock layout depends on
the block erase function, this patch couples the block erase functions with
their eraseblock layouts. struct block_eraser { struct eraseblock{ unsigned
int size; /* Eraseblock size */ unsigned int count; /* Number of contiguous
blocks with that size */ } eraseblocks[NUM_ERASEREGIONS]; int (*block_erase)
(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen);
} block_erasers[NUM_ERASEFUNCTIONS];
Corresponding to flashrom svn r719.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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Corresponding to flashrom svn r718.
Signed-off-by: Udu Ogah <putlinuxonit@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Corresponding to flashrom svn r698.
Signed-off-by: Mark Panajotovic <panajotovic.marko@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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AM29DL400BB, AM29DL400BT, AM29DL800BB, AM29DL800BT, AM29F004BB AM29F004BT,
AM29F200BB, AM29F200BT, AM29F400BB, AM29F400BT AM29F800BB, AM29F800BT,
AM29LV002BB, AM29LV002BT, AM29LV004BB AM29LV004BT, AM29LV008BB, AM29LV008BT,
AM29LV080B, AM29LV200BB AM29LV200BT, AM29LV400BB, AM29LV400BT, AM29LV800BB,
AM29LV800BT HY29F002, HY29F040A, HY29F080, HY29F400B, HY29F400T, HY29F800B
HY29F800T, HY29LV400B, HY29LV400T, HY29LV800B, HY29LV800T LH28F008BJxxPB,
LH28F008BJxxPT, LH28F008SA, LH28F008SC, LH28F800BVxxBTL LH28F800BVxxBV,
LH28F800BVxxTV, LHF00L02
Corresponding to flashrom svn r674.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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AMIC A29400T
AMIC A29400U
AMIC A29800T
AMIC A29800U
AMIC A29L004T
AMIC A29L004U
AMIC A29L008T
AMIC A29L008U
AMIC A29L040
Macronix MX29F004B
Macronix MX29F004T
Macronix MX29F022T
Macronix MX29F080
Macronix MX29F800B
Macronix MX29F800T
Macronix MX29LV081
Spansion MBM29DL400BC
Spansion MBM29DL400TC
Spansion MBM29DL800BA
Spansion MBM29DL800TA
Spansion MBM29F002BC
Spansion MBM29F002TC
Spansion MBM29F040C
Spansion MBM29F080A
Spansion MBM29F200BC
Spansion MBM29F200TC
Spansion MBM29F800BA
Spansion MBM29F800TA
Spansion MBM29LV002BC
Spansion MBM29LV002TC
Spansion MBM29LV004BC
Spansion MBM29LV004TC
Spansion MBM29LV008BA
Spansion MBM29LV008TA
Spansion MBM29LV080A
Spansion MBM29LV200BC
Spansion MBM29LV200TC
Spansion MBM29LV400BC
Spansion MBM29LV400TC
Spansion MBM29LV800BA
Spansion MBM29LV800TA
SST 49LF030A
ST M29F080
ST M29F200BB
ST M29F200BT
ST M29F400BB
ST M29F800DB
ST M29F800DT
Winbond W39L020
Winbond W39L040
Winbond W49F020
These still need to be added to flashchips.c, but if we ever encounter
them in real life, the ID->name lookup will be a lot easier.
Corresponding to flashrom svn r667.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Corresponding to flashrom svn r665.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
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The chip supports multiple erase functions, but the function we use has an
eraseblock size of 4k.
Corresponding to flashrom svn r664.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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command and not the RDID command
Unfortunately, either the datasheets are wrong or both chips have exactly
the same ID.
Corresponding to flashrom svn r662.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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Tested probing and reading only. The chip ID was already
in flashchips.h.
Corresponding to flashrom svn r648.
Signed-off-by: Hector Martin <hector@marcansoft.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Chip has now been properly tested in both my Jetway J7F5M and my EPIA-SP
(known good board). Erase and write fail. Mark these operations as bad
until i or someone else have time to fix this.
Reported by Arvid Brodin <arvidb@kth.se>.
M flashchips.c
Corresponding to flashrom svn r643.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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- VIA EPIA-M700 (reported by Jakob Bornecrantz <wallbraker@gmail.com>)
http://www.coreboot.org/pipermail/coreboot/2009-July/050416.html
- GIGABYTE GA-EX58-UD4P (reported by Warren Turkal <wt@penguintechs.org>)
http://www.coreboot.org/pipermail/coreboot/2009-June/050199.html
Mark as non-working:
- ASUS Eee PC 701 4G (reported by Uwe Hermann <uwe@hermann-uwe.de>)
There seems to be some SPI flash translation layer, likey done by the
embedded controller on the laptop (ENE KB3310).
The BIOS chip in this Eee PC model is Winbond 25X40VSIG btw.
More info: http://beta.ivancover.com/wiki/index.php/Eee_PC_Research
Mark this chip as tested:
- ST M25P40 (reported by Jakob Bornecrantz <wallbraker@gmail.com>)
http://www.coreboot.org/pipermail/coreboot/2009-July/050416.html
Other:
- Make the "Albatron PM266A" board detection print "Albatron PM266A*" as this
enable will actually work for other PM266A* boards according to libv.
However, the code was actually tested on "Albatron PM266A Pro".
- Add some more board URLs / notes.
- s/BioStar/Biostar/ as per vendor website.
- Fix typo in print.c: s/A7V8-MX SE/A7V8X-MX SE/.
Corresponding to flashrom svn r639.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Also noted as a comment if an FWH/LPC chip supports A/A Mux mode.
Corresponding to flashrom svn r634.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Thanks to Michael Stapelberg for the report.
Corresponding to flashrom svn r622.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Thanks to Simon Brown for the report.
Corresponding to flashrom svn r621.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Thanks to Harald Gutmann for testing.
Corresponding to flashrom svn r620.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Thanks to Wangji for testing and pointing out that EN25* chips were
unsupported, which was handled in r580 and r592.
Corresponding to flashrom svn r619.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Also, add support for the Silicon Image 3112(A) SATA controller.
Both have been tested by Andrew Morgan <ziltro@ziltro.com> on hardware
and work fine.
Corresponding to flashrom svn r613.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Andrew Morgan <ziltro@ziltro.com>
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has a huge chunk of chip and vendor IDs in the middle
Split them out into a separate flashchips.h and adjust #include wherever needed.
Corresponding to flashrom svn r594.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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EN25B32, EN25B64
EN25F40, EN25F80, EN25F16 Add support for EN25P05, EN25P10, EN25P20, EN25P40,
EN25P80, EN25P16, EN25P32, EN25P64 EN25D16 EN25F05, EN25F10, EN25F20, EN25F32
Corresponding to flashrom svn r592.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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I sucessfully tested all operations on a Pm29F002T chip. The Pm29F002B is
untested but I assume it should also work.
Corresponding to flashrom svn r590.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Corresponding to flashrom svn r588.
Signed-off-by: Mateusz Murawski <matowy@tlen.pl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Add timing info to some flash chips.
Corresponding to flashrom svn r584.
Signed-off-by: Mateusz Murawski <matowy@tlen.pl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Some IDs were already in flash.h. EN25B05 EN25B10 EN25B20 EN25B40 EN25B80
EN25B16 EN25B32 EN25B64 EN25F40 EN25F80 EN25F16 EN25P* are supported as well,
but they seem to be identical to EN25B.
Corresponding to flashrom svn r580.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
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Corresponding to flashrom svn r576.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
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AT49F002, AMIC A29040B, A49LF040A
EMST F49B002UA, EON EN29F002, Intel 28F001BX-B, 28F001BX-T, Winbond W29C020C
and W29C040P. Checked from datasheets. A49LF040A is LPC, others parallel.
Corresponding to flashrom svn r574.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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This eliminates the conflicting delay requirements for old and new chips
with the same probing sequence.
Corresponding to flashrom svn r569.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Also, add Atmel AT29C512 support.
Both are tested on hardware by Maciej Pijanka.
Corresponding to flashrom svn r566.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Corresponding to flashrom svn r564.
Signed-off-by: Mateusz Murawski <matowy@tlen.pl>
Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>
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Right now, the annotation only differentiates between SPI and non-SPI. Anyone
who knows more about a specific flash chip should feel free to update it.
The existing flashbus variable was abused to denote the SPI controller type.
Use an aptly named variable for that purpose. Once this patch is merged,
the chipset/programmer init functions can set supported flash chip types
and flashrom can automatically select only matching probe/read/erase/write
functions. A side benefit of that will be the elimination of the Winbond
W29EE011 vs. AMIC A49LF040A conflict.
Corresponding to flashrom svn r556.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Erase & write support wont be this easy - the chips need 12V Vpp
(needs a hardware hack or a supporting mb) and they have a very weird
layout and are old.
Corresponding to flashrom svn r555.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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very long name and currently even breaks -L output
We could of course fix that, but we already use short / abbreviated names
for other vendors (AMD, ST, SST, PMC) so do it for TI also.
Corresponding to flashrom svn r552.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Corresponding to flashrom svn r550.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
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- ASUS P5B-Deluxe (reported by Andrew Paprocki)
- ASUS P6T Deluxe V2 (reported by Aldrik Dunbar)
- GIGABYTE GA-6ZMA (reported by Urja Rannikko)
- Intel EP80759 (reported by Stephan GUILLOUX)
- MSI MS-7345 (P35 Neo2-FIR) (reported by Onno)
- MSI MS-7168 (Orion) (reported by ubuntosaure)
- Supermicro H8QC8 (reported by Victor Zele)
Mark the following boards as 'known-bad' (they likely require a write-enable):
- Abit IS-10 (reported by deejkuba)
- ASUS P5B (reported by Henning Fleddermann)
- ASUS P5BV-M (reported by Bernhard M. Wiedemann)
- Boser HS-6637 (reported by Mark Robinson)
Also, mark the Winbond W39V040A as fully tested (report by ubuntosaure).
Corresponding to flashrom svn r542.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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- Mention that we'd like to have -V output for all operations
which were tested by the user.
- Mention that we'd like to know the exact mainboard vendor/name.
Corresponding to flashrom svn r540.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Corresponding to flashrom svn r539.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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I tested all operations on hardware.
Corresponding to flashrom svn r538.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Corresponding to flashrom svn r526.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
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[PATCH] tested SST39VF010
Self-ack is fine for test reports.
Rudolf Marek wrote:
Corresponding to flashrom svn r525.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
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3C90xC ones don't)
This is tested on hardware. Also, add initial support for the Atmel AT29C010A
chip (which I inserted in a 3COM 3C90xB card for testing). It can be detected,
read works, erase works, but write will need some additional code (will post
in another patch later).
Corresponding to flashrom svn r520.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Downgrade the chips from 256-byte writes to 1-byte writes. This fixes
writing to them on ICH/VIA SPI masters.
Corresponding to flashrom svn r504.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>
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Thanks to Mateusz for testing and reporting!
Corresponding to flashrom svn r503.
Signed-off-by: Mateusz Murawski <matowy@tlen.pl>
Acked-by: Peter Stuge <peter@stuge.se>
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Tested with 3COM 3C905C: EtherLink 10/100 PCI (TX)
http://www.coreboot.org/pipermail/coreboot/2009-May/048163.html
Corresponding to flashrom svn r502.
Signed-off-by: Mateusz Murawski <matowy@tlen.pl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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