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author | Uwe Hermann <uwe@hermann-uwe.de> | 2008-10-18 21:14:13 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2008-10-18 21:14:13 +0000 |
commit | ba4bbd54ba3169dd5e81fcf867365e23caa907ba (patch) | |
tree | 8be1ee454d786c1aae0ea45be068e22b2a7c70a5 /spi.c | |
parent | 3eb2d1e9f1d53d4df699b741c151a66b904dd1a4 (diff) | |
download | flashrom-ba4bbd54ba3169dd5e81fcf867365e23caa907ba.zip flashrom-ba4bbd54ba3169dd5e81fcf867365e23caa907ba.tar.gz |
Coding-style fixes for flashrom, partly indent-aided
Corresponding to flashrom svn r326 and coreboot v2 svn r3669.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Diffstat (limited to 'spi.c')
-rw-r--r-- | spi.c | 96 |
1 files changed, 53 insertions, 43 deletions
@@ -29,37 +29,41 @@ #include "flash.h" #include "spi.h" - void spi_prettyprint_status_register(struct flashchip *flash); -int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) +int spi_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) { switch (flashbus) { case BUS_TYPE_IT87XX_SPI: - return it8716f_spi_command(writecnt, readcnt, writearr, readarr); + return it8716f_spi_command(writecnt, readcnt, writearr, + readarr); case BUS_TYPE_ICH7_SPI: case BUS_TYPE_ICH9_SPI: case BUS_TYPE_VIA_SPI: - return ich_spi_command(writecnt, readcnt, writearr, readarr); + return ich_spi_command(writecnt, readcnt, writearr, readarr); default: - printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__); + printf_debug + ("%s called, but no SPI chipset/strapping detected\n", + __FUNCTION__); } return 1; } static int spi_rdid(unsigned char *readarr, int bytes) { - const unsigned char cmd[JEDEC_RDID_OUTSIZE] = {JEDEC_RDID}; + const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; if (spi_command(sizeof(cmd), bytes, cmd, readarr)) return 1; - printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]); + printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], + readarr[2]); return 0; } static int spi_res(unsigned char *readarr) { - const unsigned char cmd[JEDEC_RES_OUTSIZE] = {JEDEC_RES, 0, 0, 0}; + const unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; if (spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr)) return 1; @@ -69,7 +73,7 @@ static int spi_res(unsigned char *readarr) void spi_write_enable() { - const unsigned char cmd[JEDEC_WREN_OUTSIZE] = {JEDEC_WREN}; + const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; /* Send WREN (Write Enable) */ spi_command(sizeof(cmd), 0, cmd, NULL); @@ -77,7 +81,7 @@ void spi_write_enable() void spi_write_disable() { - const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = {JEDEC_WRDI}; + const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; /* Send WRDI (Write Disable) */ spi_command(sizeof(cmd), 0, cmd, NULL); @@ -110,10 +114,10 @@ static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) model_id = (readarr[1] << 8) | readarr[2]; } - printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id); + printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, + model_id); - if (manuf_id == flash->manufacture_id && - model_id == flash->model_id) { + if (manuf_id == flash->manufacture_id && model_id == flash->model_id) { /* Print the status register to tell the * user about possible write protection. */ @@ -130,13 +134,14 @@ static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) return 0; } -int probe_spi_rdid(struct flashchip *flash) { +int probe_spi_rdid(struct flashchip *flash) +{ return probe_spi_rdid_generic(flash, 3); } /* support 4 bytes flash ID */ -int probe_spi_rdid4(struct flashchip *flash) { - +int probe_spi_rdid4(struct flashchip *flash) +{ /* only some SPI chipsets support 4 bytes commands */ switch (flashbus) { case BUS_TYPE_ICH7_SPI: @@ -181,7 +186,7 @@ int probe_spi_res(struct flashchip *flash) uint8_t spi_read_status_register() { - const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR}; + const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; unsigned char readarr[JEDEC_RDSR_INSIZE]; /* Read Status Register */ @@ -194,17 +199,17 @@ uint8_t spi_read_status_register() void spi_prettyprint_status_register_common(uint8_t status) { printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); + "%sset\n", (status & (1 << 5)) ? "" : "not "); printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); + "%sset\n", (status & (1 << 4)) ? "" : "not "); printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); + "%sset\n", (status & (1 << 3)) ? "" : "not "); printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); + "%sset\n", (status & (1 << 2)) ? "" : "not "); printf_debug("Chip status register: Write Enable Latch (WEL) is " - "%sset\n", (status & (1 << 1)) ? "" : "not "); + "%sset\n", (status & (1 << 1)) ? "" : "not "); printf_debug("Chip status register: Write In Progress (WIP/BUSY) is " - "%sset\n", (status & (1 << 0)) ? "" : "not "); + "%sset\n", (status & (1 << 0)) ? "" : "not "); } /* Prettyprint the status register. Works for @@ -214,9 +219,9 @@ void spi_prettyprint_status_register_common(uint8_t status) void spi_prettyprint_status_register_st_m25p(uint8_t status) { printf_debug("Chip status register: Status Register Write Disable " - "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); printf_debug("Chip status register: Bit 6 is " - "%sset\n", (status & (1 << 6)) ? "" : "not "); + "%sset\n", (status & (1 << 6)) ? "" : "not "); spi_prettyprint_status_register_common(status); } @@ -235,12 +240,12 @@ void spi_prettyprint_status_register_sst25vf016(uint8_t status) "all", "all" }; printf_debug("Chip status register: Block Protect Write Disable " - "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); + "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); printf_debug("Chip status register: Auto Address Increment Programming " - "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not "); + "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not "); spi_prettyprint_status_register_common(status); printf_debug("Resulting block protection : %s\n", - bpt[(status & 0x1c) >> 2]); + bpt[(status & 0x1c) >> 2]); } void spi_prettyprint_status_register(struct flashchip *flash) @@ -265,11 +270,11 @@ void spi_prettyprint_status_register(struct flashchip *flash) break; } } - + int spi_chip_erase_c7(struct flashchip *flash) { - const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = {JEDEC_CE_C7}; - + const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 }; + spi_disable_blockprotect(); spi_write_enable(); /* Send CE (Chip Erase) */ @@ -289,7 +294,7 @@ int spi_chip_erase_c7(struct flashchip *flash) */ int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) { - unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = {JEDEC_BE_D8}; + unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8 }; cmd[1] = (addr & 0x00ff0000) >> 16; cmd[2] = (addr & 0x0000ff00) >> 8; @@ -308,7 +313,7 @@ int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_sector_erase(const struct flashchip *flash, unsigned long addr) { - unsigned char cmd[JEDEC_SE_OUTSIZE] = {JEDEC_SE}; + unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE }; cmd[1] = (addr & 0x00ff0000) >> 16; cmd[2] = (addr & 0x0000ff00) >> 8; cmd[3] = (addr & 0x000000ff); @@ -330,7 +335,8 @@ int spi_sector_erase(const struct flashchip *flash, unsigned long addr) */ void spi_write_status_register(int status) { - const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = {JEDEC_WRSR, (unsigned char)status}; + const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = + { JEDEC_WRSR, (unsigned char)status }; /* Send WRSR (Write Status Register) */ spi_command(sizeof(cmd), 0, cmd, NULL); @@ -338,10 +344,11 @@ void spi_write_status_register(int status) void spi_byte_program(int address, uint8_t byte) { - const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = {JEDEC_BYTE_PROGRAM, - (address>>16)&0xff, - (address>>8)&0xff, - (address>>0)&0xff, + const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = { + JEDEC_BYTE_PROGRAM, + (address >> 16) & 0xff, + (address >> 8) & 0xff, + (address >> 0) & 0xff, byte }; @@ -364,7 +371,8 @@ void spi_disable_blockprotect(void) void spi_nbyte_read(int address, uint8_t *bytes, int len) { - const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ, + const unsigned char cmd[JEDEC_READ_OUTSIZE] = { + JEDEC_READ, (address >> 16) & 0xff, (address >> 8) & 0xff, (address >> 0) & 0xff, @@ -376,7 +384,6 @@ void spi_nbyte_read(int address, uint8_t *bytes, int len) int spi_chip_read(struct flashchip *flash, uint8_t *buf) { - switch (flashbus) { case BUS_TYPE_IT87XX_SPI: return it8716f_spi_chip_read(flash, buf); @@ -385,7 +392,9 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf) case BUS_TYPE_VIA_SPI: return ich_spi_read(flash, buf); default: - printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__); + printf_debug + ("%s called, but no SPI chipset/strapping detected\n", + __FUNCTION__); } return 1; @@ -401,9 +410,10 @@ int spi_chip_write(struct flashchip *flash, uint8_t *buf) case BUS_TYPE_VIA_SPI: return ich_spi_write(flash, buf); default: - printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__); + printf_debug + ("%s called, but no SPI chipset/strapping detected\n", + __FUNCTION__); } return 1; } - |