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* Remove unreachable codeJukka Ojanen2014-11-131-3/+5
* Enable compiler warningsJukka Ojanen2014-11-131-4/+11
* benchFFTS is computing the correct answer with theseJukka Ojanen2014-11-111-24/+24
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| * Damn AT&T syntaxfix_generate_size4_base_caseJukka Ojanen2014-11-111-24/+24
* | generate_leaf_init, generate_leaf_ee, generate_leaf_eo, generate_leaf_oe and ...Jukka Ojanen2014-11-112-119/+521
* | Merge commit '219d8edbde01596d3426915bfb93ea6105a1eae7'Jukka Ojanen2014-11-111-4/+13
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| * | Rename x64_movhlps_reg_reg to x64_sse_movhlps_reg_regJukka Ojanen2014-11-111-4/+4
| * | Add x64_movsxd_reg_memindexJukka Ojanen2014-11-111-0/+9
* | | Replace movdqa with movaps which is one byte shorter. Don't need RDI register...Jukka Ojanen2014-11-103-79/+71
* | | Merge commit '11fbf3ec5a1a7120c5f790300d9eaf12adde8296'Jukka Ojanen2014-11-101-34/+57
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| * Add size parameter to emit_sse_reg_membase_op2/emit_sse_membase_reg_op2Jukka Ojanen2014-11-101-34/+57
* | Generate function in "generate_size4_base_case"Jukka Ojanen2014-11-101-10/+79
* | Removed last bits of magic from "generate_size8_base_case".Jukka Ojanen2014-11-092-140/+122
* | Merge commit '8ef1d3a20ab69ef66f8506e61a08d4cfcc82d3f9'Jukka Ojanen2014-11-091-32/+34
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| * Replace amd64 with x64 in 32 bit header, which means that some macros are in ...Jukka Ojanen2014-11-091-32/+34
* | Replace "magic bytes" with various macrosJukka Ojanen2014-11-091-211/+59
* | Merge commit 'f342eb3215720f9c2fe621e3445484d55c00ff3d'Jukka Ojanen2014-11-091-5/+39
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| * Added x64_sse_movaps_memindex_reg and x64_sse_movaps_reg_memindexJukka Ojanen2014-11-091-5/+39
* | Replace SHUFPS with x64_sse_shufps_reg_reg_immJukka Ojanen2014-11-091-79/+9
* | Replace MULPS with x64_sse_mulps_reg_regJukka Ojanen2014-11-091-31/+12
* | Replace MOVDQA with x64_sse_movdqa_reg_membase/64_sse_movdqa_membase_regJukka Ojanen2014-11-091-98/+20
* | Merge commit '89560561f49db1b5ed838b934256a2e38566da88'Jukka Ojanen2014-11-091-0/+9
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| * Add SSE opcode "movdqa"Jukka Ojanen2014-11-091-0/+9
* | Replace MOVAPS with x64_sse_movaps_reg_membaseJukka Ojanen2014-11-091-76/+1
* | Replace SUBPS with x64_sse_subps_reg_regJukka Ojanen2014-11-091-30/+12
* | Replace ADDPS with x64_sse_addps_reg_regJukka Ojanen2014-11-091-30/+13
* | Replace XORPS with x64_sse_xorps_reg_regJukka Ojanen2014-11-091-21/+4
* | Merge commit '757b6eb0e7a5742ffd23b721f2fe2e041ffd1069'Jukka Ojanen2014-11-091-6/+6
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| * Again default to "__default_codegen__"Jukka Ojanen2014-11-091-6/+6
* | Replace XOR2 with x86_clear_reg, MOV_D with x64_mov_membase_reg/x86_mov_reg_m...Jukka Ojanen2014-11-092-119/+19
* | Replace MOV_I with x86_mov_reg_imm, SHIFT with x86_shift_reg_imm, CALL with x...Jukka Ojanen2014-11-092-120/+39
* | Replace add/sub immediate value with x64_alu_reg_imm_size_bodyJukka Ojanen2014-11-092-54/+7
* | Replace register names with new definitionsJukka Ojanen2014-11-082-102/+73
* | Merge commit 'd1896e187eed7dbdd18ba34c0fe68025c678c18c'Jukka Ojanen2014-11-082-113/+114
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| * If nothing is defined, then it's "__default_codegen__"Jukka Ojanen2014-11-082-113/+114
* | Wheel is already invented. Adding part of Mono project, https://github.com/mo...Jukka Ojanen2014-11-0852-0/+22754
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| * Replace glib.h with stdint.h for standard C99Jukka Ojanen2014-11-081-16/+16
| * Replace amd64 with x64Jukka Ojanen2014-11-081-967/+967
| * Rename amd64-codegen.h to x64-codegen.hJukka Ojanen2014-11-082-1/+1
| * Rename folder amd64 to x64Jukka Ojanen2014-11-083-0/+0
| * Added README and LICENSE text. Rebuild ChangeLog from Git logsJukka Ojanen2014-11-083-1096/+4746
| * [runtime] Remove an unused interpreter file.Zoltan Varga2014-09-131-18/+0
| * [cleanup] Remove more old files.Rodrigo Kumpera2014-09-098-2772/+3
| * [runtime] Remove the interpreter.Rodrigo Kumpera2014-09-013-22/+0
| * Architectural level set to z10 instruction setNeale Ferguson2014-06-041-13/+199
| * Add .gitignore file in mono/arch/arm64.Alex Rønne Petersen2014-04-301-0/+6
| * [arm64] Add JIT support.Zoltan Varga2014-04-221-0/+3
| * [arm64] Add basic port infrastructure.Zoltan Varga2014-04-222-1/+1
| * [jit] Implement support for atomic intrinsics on arm.Zoltan Varga2014-04-011-0/+12
| * [arch]Add cvtsi2ss to amd64 codegen.Rodrigo Kumpera2013-12-111-0/+4
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