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* run preprocessor on DSDT of D945GCLF, otherwise Stefan Reinauer2010-01-181-1/+2
| | | | | | | | | | | smart iasl will segfault. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* get rid of Kconfig warning.Stefan Reinauer2010-01-181-2/+2
| | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Roda RK886EX a.k.a Rocky III+ ruggedised notebookStefan Reinauer2010-01-1733-0/+4715
| | | | | | | | | | | | http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Initial PCIe tuning: Enable Active State Power Management (ASPM)Stefan Reinauer2010-01-171-2/+10
| | | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Texas Instruments Cardbus+Firewire bridge TI PCI7420Stefan Reinauer2010-01-1711-0/+379
| | | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Renesas M3885x Embedded ControllerStefan Reinauer2010-01-178-0/+153
| | | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the SMSC LPC47n227 SuperI/O chipStefan Reinauer2010-01-178-0/+604
| | | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ICH7 updateStefan Reinauer2010-01-176-38/+175
| | | | | | | | | | | | | | | | | | * change the code to use macros names instead of constants in many places * SMI/ACPI: rework power-off code to work with old Linux kernels (2.6.12.x) * SMI: Add support for mainboard GPI handler * SMI: immediate power-off on power button press, if OSPM is not active * Add fix for some USB errata * Some register tweaks for mobile systems * Enable configure SCI on interrupt 9 correctly. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support a few more i945 variants. With this framework in place it shouldStefan Reinauer2010-01-172-223/+441
| | | | | | | | | | | | be possible to support i955 and i975 relatively easy, too. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* coreboot has 13 instances of IOAPIC setup distributed across a lotStefan Reinauer2010-01-1624-928/+238
| | | | | | | | | | | | | of components. This patch is a rewrite of the generic IOAPIC setup code. Additionally it drops the other 12 instances of IOAPIC setup code and makes the components use the generic code. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* coreboot used to have two different "APIs" for memory accesses:Stefan Reinauer2010-01-1632-219/+264
| | | | | | | | | | | | | | | | | | | | read32(unsigned long addr) vs readl(void *addr) and write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr) read32 was only available in __PRE_RAM__ stage, while readl was used in stage2. Some unclean implementations then made readl available to __PRE_RAM__ too which results in really messy includes and code. This patch fixes all code to use the read32/write32 variant, so that we can remove readl/writel in another patch. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Intel D945GCLF: Enable SMI and ACPI in Kconfig, too (it's enabled in newconfig)Stefan Reinauer2010-01-162-2/+6
| | | | | | | | | | | and guard SMI specific parts of the ACPI code. (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* (trivial) cosmetics for i82801gx cmos failover.Stefan Reinauer2010-01-161-4/+3
| | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* * drop reset files from 945 mainboards (and use southbridge specific reset)Stefan Reinauer2010-01-1614-323/+41
| | | | | | | | | | | | | * drop debug.c files from 945 mainboards (and share it in the northbridge code) * adapt the mainboard and auto.c files for above changes. Rather trivial Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make internal functions static in speedstep ACPI generation code.Stefan Reinauer2010-01-161-2/+2
| | | | | | | | | | (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix stack base for Atom CPUs, the resume mechanism (cbmem etc) expects this.Stefan Reinauer2010-01-161-4/+4
| | | | | | | | | | | This unifies the base with Core and Core 2 CPUs. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Micro-optimization: movl $0 --> xorl.Stefan Reinauer2010-01-162-5/+5
| | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* new microcode for Intel Core 2(tm) CPUsStefan Reinauer2010-01-169-1168/+1168
| | | | | | | | | | | (taken from Intel's Linux microcode release) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* RTC: Don't drop the alpha specific code but get it in shape for our Kconfig ↵Stefan Reinauer2010-01-161-4/+4
| | | | | | | | | | | | scheme. (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make qemu use the udelay function in src/pc80/udelay_io.cPatrick Georgi2010-01-113-19/+2
| | | | | | | | | | | instead of the equivalent copy in src/cpu/emulation/qemu-x86/northbridge.c. Also, delete the copy. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* - Makefile.romccboard.inc supports tinybootblock romcc boards, too.Patrick Georgi2010-01-085-145/+20
| | | | | | | | | | | | | - via/epia-cn is a romcc board, not a CAR board. (Thanks Kevin, for the report) - Make emulation/qemu-x86, dell/s1850, via/epia-cn use Makefile.romccboard.inc - New flag: BIG_BOOTBLOCK, which is always the inverse of tinybootblock Suitable for Makefile.inc rules (foo-$(CONFIG_BIG_BOOTBLOCK) += ...) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move fam10 temp files from build/ to build/northbridge/amd/amdfam10/ Trivial.Myles Watson2010-01-061-18/+18
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix amdht on newer compilers.Patrick Georgi2010-01-061-1/+1
| | | | | | | | | | | We were lucky with friendly compilers. Now they're assuming too much. Identified-by: Myles Watson <mylesgw@gmail.com> Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Kconfig builds all boards now.Patrick Georgi2010-01-0612-51/+103
| | | | | | | | | | | | | | | | | | | This patch also aligns the configuration of a couple of boards more closely to what newconfig does. Also, the romstrap inc/lds files are declared in the Makefiles of the southbridges they belong to, instead of some global file. AMD CPUs have their own timer functions, so disable UDELAY_IO for them and set HAVE_INIT_TIMER as appropriate, same for emulation/qemu-x86. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* - Let AMD CAR code pick the right XIP areaRudolf Marek2010-01-054-10/+19
| | | | | | | | | | | | | for tinybootblock - move asus/m2v-mx_se to tinybootblock - Add romstrap for via southbridge to tinybootblock-bootblock Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* * Explicitly add __PRE_RAM__ where it should be added.Stefan Reinauer2010-01-0575-5/+80
| | | | | | | | | | | | | | * Don't implicitly add __PRE_RAM__ in romcc. Fixes intel/xe7501devkit Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* - Fix UDELAY options and HAVE_INIT_TIMER [kconfig]Patrick Georgi2010-01-0412-18/+34
| | | | | | | | | | | | | | | | (defaults to UDELAY_IO again, like newconfig) - Use UDELAY_TSC on Via C7 [kconfig] - Support Tinybootblock on Intel CPUs - set XIP location correctly for Tinybootblock on Intel - provide correct XIP location in Tinybootblock configuration - Make kontron/986lcd-m use Tinybootblock - Some kconfig fixes to kontron/986lcd-m [kconfig] Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* - use LAPIC timer if selected (instead of TSC all the time) [kconfig]Patrick Georgi2010-01-045-3/+5
| | | | | | | | | | | - uncomment commented out intel socket [kconfig] - HAVE_MOVNTI is a property of the cpu [kconfig] Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* improve debug output.Stefan Reinauer2010-01-031-1/+1
| | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* romcc:Patrick Georgi2009-12-3113-49/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Set __PRE_RAM__ define per default - Properly handle ignored (#ifdef'd out) #include lines amd/serengeti_cheetah_fam10: - write ACPI files to $(obj) instead of the top dir (alias $(CURDIR)) tinybootblock: - provide a way to define code that should be added to the bootblock, to map the entire ROM for use by CBFS amd/model_fxx, amd/model_10xxx: - add CONFIG_SSE walkcbfs.S: - eliminate the use of two registers, to make space for romcc to wiggle amd/serengeti_cheetah_fam10: - use the enable_rom framework. not entirely functional yet Boot-tested on emulation/qemu-x86 Build-tested on amd/serengeti_cheetah_fam10 amd/serengeti_cheetah_fam10 fails in amdht/ somewhere, but builds Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* trival. All the changes is about comment and spaces.Zheng Bao2009-12-28178-897/+2600
| | | | | | | | | | | | | | | | | | | In superio folder. 1. Delete trailing white spaces. 2. Change the // comment to /* */. 3. Add some copyright header. 4. reindent. 5. delete multi blank lines. I tried my best to find them. If anything left, please fix it or tell me. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix technexion tim5690 build failure - REALMODE option required for x86.c ↵Marc Jones2009-12-231-0/+2
| | | | | | | | | | | mainboard function to be built. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* newconfig compilation failed withStefan Reinauer2009-12-231-0/+1
| | | | | | | | | | | (.text+0x4989): undefined reference to `vgabios_init' Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add mainboard x86emu interrupt function support. Add tim5690 VGA BIOS ↵Libra Li2009-12-236-15/+268
| | | | | | | | | | | functions: int15 getting LCD panel ID. Signed-off-by: Libra Li <libra.li@technexion.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Tiny Bootblock, step 1/n.Patrick Georgi2009-12-2310-37/+291
| | | | | | | | | | | Introduce the tiny bootblock infrastructure and use it on QEmu. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Allow user to specify the size of a newly created cbfs imagePatrick Georgi2009-12-211-1/+1
| | | | | | | | | | | | | | | | to be stated in kilobytes or megabytes. Usage is cbfstool coreboot.rom create 1048576 coreboot.bootblock cbfstool coreboot.rom create 1024k coreboot.bootblock cbfstool coreboot.rom create 1m coreboot.bootblock to get an 1048576 bytes = 1024kb = 1mb image. Kconfig also uses this instead of calculating bytes from kilobytes itself. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make coreboot load VSA from CBFS on amd/gx2.Patrick Georgi2009-12-211-11/+5
| | | | | | | | | | | | | | | | | | | | You have to convert the VSA bios image to ELF using the following commands (assuming i386/32bit binutils, if in doubt, use crossgcc's i386-elf-* tools): objcopy --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 vsa.binary vsa.o ld -e 0x60020 --section-start .data=0x60000 vsa.o -o vsa.elf Then, after build, use cbfstool coreboot.rom add-stage vsa.elf vsa l to add it to the image. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Clean up amd/dbm690t and kontron/986lcd-m some more (notPatrick Georgi2009-12-183-12/+33
| | | | | | | | | | fully). Also fix the kconfig build for HAVE_ACPI_RESUME. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make "KBuild report" a bit happierStefan Reinauer2009-12-171-11/+0
| | | | | | | | | | | | | | - drop some unused options from "newconfig" - filter some Kconfig only options from the report - drop targets directory of a non existent mainboard. (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The drivers for the k8t890 weren't being built. Increased heapsize.Myles Watson2009-12-142-7/+15
| | | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Push VSA into CBFS for amd/lx systems. It's not hooked up toPatrick Georgi2009-12-101-11/+5
| | | | | | | | | | | | | | | | | | | | | | | the build system yet, so some additional steps are necessary. It's not that bad, given that the code didn't work before. You have to convert the VSA bios image to ELF using the following commands (assuming i386/32bit binutils, if in doubt, use crossgcc's i386-elf-* tools): objcopy --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 vsa.binary vsa.o ld -e 0x60020 --section-start .data=0x60000 vsa.o -o vsa.elf Then, after build, use cbfstool coreboot.rom add-stage vsa.elf vsa l to add it to the image. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Trivial fixes for kconfig. They fix all non-fam10 build failures.Myles Watson2009-12-0212-22/+29
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Trivial fix for kconfig socket 441 (typo was 411) so that d945gclf builds.Myles Watson2009-12-022-2/+2
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Not all boards cope with automatically sized bootblocks, leading to 4GBPatrick Georgi2009-12-011-13/+1
| | | | | | | | | | | | | images due to the "helpful" 4GB rollover behaviour of ld(1). Back out r4961, something like this should go in eventually, but more completely tested and working. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Atom only supports 32bit MTRRs (trivial)Stefan Reinauer2009-12-011-1/+1
| | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Trivial. SCH4304 and SCH4307 have the same device id.Zheng Bao2009-12-011-1/+1
| | | | | | | | | | Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the SMSC SCH4304 Super I/O.Zheng Bao2009-11-301-0/+2
| | | | | | | | | | Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Maciej Pijanka tried to get the Biostar M6TLD running, and created a patch forMaciej Pijanka2009-11-2811-0/+877
| | | | | | | | | | | | 440lx using the 440bx code as a template. Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Eliminate special case id.inc/id.lds in favor of a configuration variable ↵Patrick Georgi2009-11-2757-205/+140
| | | | | | | | | | | | | | | ID_SECTION_OFFSET which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative) where necessary (if romstraps get in the way). For Kconfig, the special case is set per southbridge (as these define the necessity for this workaround), for newconfig it's added to each single board. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Let ld(1) calculate the required size for code in the bootblockMaciej Pijanka2009-11-271-1/+13
| | | | | | | | | | automatically. Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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