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* vendorcode/amd: 64bit fixesStefan Reinauer2015-10-3014-59/+65
| | | | | | | | Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* x86: Drop -Wa,--divideStefan Reinauer2015-07-071-3/+3
| | | | | | | | | | Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10819 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* vendorcode/amd/agesa: Remove UCODE_VS_FLAG() macro unused variableEdward O'Callaghan2015-01-142-5/+1
| | | | | | | | | | | | Remove useless AGESA microcode macro that leads to unused variable warnings. Change-Id: Ia21bfc758f81e349bdd0bfd185df75e8b1898336 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8200 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
* AMD Trinity: Update SMU firmware from 10.9 to 10.14Zheng Bao2014-12-181-1285/+2586
| | | | | | | | | | | | | | The first dword in FirmwareTN has been changed from 0xa0009 to 0xa000e. The FirmwareTNHeader is not called by any one in latest PI. It seems to be useless for now. Change-Id: Ic7a20e0bcca8de0b56c7bc5d01e0ce86347bde21 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
* amd/agesa/f*/Lib/amdlib.c: Integer overflow in loop constructEdward O'Callaghan2014-12-161-5/+13
| | | | | | | | | | | | | | | | | | | As is the case in commit: 3312ed7 amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop construct The semantics of this loop relies on an integer overflow in Index >=0 that implies a return value of (UINT8)-1 which around wraps to 0xFF, or VOLT_UNSUPPORTED. Also fix an infinite loop. Change-Id: Iced3eff3ae7b8935db3bdd6147372cf3b540883c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7676 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* vendorcode/amd/agesa/f1{5,5tn,6kb}: Silence empty loop warnEdward O'Callaghan2014-12-071-1/+4
| | | | | | | | | | | Add decorations to specify that empty loop is intended so. Change-Id: Ia3e40d341eca5e26da3832edc733cf1ccc96c136 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Found-by: Clang Reviewed-on: http://review.coreboot.org/7688 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* vendorcode/amd/agesa/f15tn/*/F15TnMsrTables.c: Topology Extensions SupportEdward O'Callaghan2014-12-071-1/+1
| | | | | | | | | | | | | | | Topology Extensions Support (bit 54 of 0xC0011005) applies to PACKAGE_TYPE_FS1r2 also. Rids us of: "Re-enabling disabled Topology Extensions Support" showing up in dmesg. Change-Id: Id123fa9632936c150cf1aebc4d34b404a4398ead Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7671 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* vendorcode/amd/agesa: Remove unused helper.c fileAlexandru Gagniuc2014-12-062-69/+0
| | | | | | | | | | | The contents of these files were guarded by a check for the _MSC_VER macro, which we don't use. Change-Id: Ic595c8e6284c54e1449cf21e0cebee8c9ce7c682 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7670 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
* vendorcode/amd/agesa: Make Porting.h common between familiesEdward O'Callaghan2014-12-062-282/+1
| | | | | | | | Change-Id: Ica17b2452498f30b710533caf610c9f0c1a0452c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7594 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* vendorcode/amd/agesa/f15tn: Fix GnbIommuScratch in AGESA compilationEdward O'Callaghan2014-12-063-1/+21
| | | | | | | | | | | | Missing IOMMU support is missing from the libagesa Makefile, it also lacks a header with type-signature and a few bad typecast issues. Change-Id: I7f2ad2104de9baaa66dbb6ffeb0f2b4d35fa5c16 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Co-Author: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/7642 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* vendorcode/amd/agesa/fam15tn: Clean #includes in public headersAlexandru Gagniuc2014-12-0629-52/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | Right now, coreboot code using AGESA headers can only build if all the AGESA path are given to the compiler via the "-I" option. This is sub- optimal, as it requires us to have every AGESA source directory specified as a compiler include path. This pollutes our global include paths. We restrict the compiler include paths to only allow "AGESA_ROOT/" and "AGESA_ROOT/Include". We then modify the AGESA headers to specify non-local include files relative to "AGESA_ROOT/Include". We use the convention that includes relative to the directory of the header are included as "path/to/header.h", while includes relative to AGESA_ROOT are included as <path/to/header.h>. This change allows building coreboot code based on AGESA with the limited subset of include paths, but does not allow AGESA itself to build with this restricted subset. Change-Id: I31102273c8caa8d6b1d80774bfd35711825bec03 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5424 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
* vendorcode/amd/agesa/f15tn: Trim out ASCII art in GnbIommuScratch.cEdward O'Callaghan2014-12-051-30/+2
| | | | | | | | | | TL;DR ASCII art that sucks, remove it. Change-Id: I424736b040fe019bba6155de76903225a266760d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7641 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* vendorcode/amd/agesa/f*/cpcar.in: Remove non-GCC CAR implementationEdward O'Callaghan2014-12-041-1529/+0
| | | | | | | | | | | | We don't actually use nor support these as our implementation makes use of gcccar.inc. They maybe useful as a reference for history so lets keep them in version history. Change-Id: I388251dead449dde14283e57db39c37982d947b2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7596 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Use AMD_F15_TN_A0 define in FTnLogicalIdTables.cEdward O'Callaghan2014-11-281-1/+1
| | | | | | | | | Change-Id: I6b20ded866fa0418bd24ce9eef3775557c2feec7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7562 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* vendorcode/amd/agesa: Use F15TN AGESA for F15RLEdward O'Callaghan2014-11-271-0/+4
| | | | | | | | | | | | | | | | | For the moment we make use of Trinity f15tn AGESA for Richland f15rl support until we have properly worked out the discrepancies. Adds RL-A1 Richland stepping cpuid to F15TnLogicalIdTables lookup. We later wish to merge f15tn and f15rl support into the AGESA in any case. Change-Id: Ia9070d4e392ce7eb912771d1c7b3ef1440f8e8a8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7559 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
* vendorcode/amd/agesa/f15?tn: Reduce useless differencesSara Lelliott2014-11-204-99/+103
| | | | | | | | | | | Reduce inconsequential differences between fam15 and fam15tn to better prepare for possible merger. Change-Id: I016aa1a4cc45553d51190988d48c8a54cfd85f5a Signed-off-by: Sara Lelliott <sara@jupitercrash.org> Reviewed-on: http://review.coreboot.org/7503 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* vendorcode/amd/agesa/f15tn: Fix assembly bugsDamien Zammit2014-11-191-1/+1
| | | | | | | | | | Found missing '$' symbol on variable. Change-Id: I748c315adc44598e16283f8e629be0ecfe9cb6a9 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7514 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* vendorcode/amd/agesa/f15tn: Remove extraneous bracketDamien Zammit2014-11-191-2/+2
| | | | | | | | | | | Found an extra bracket that appears it should not be there. Change-Id: I66b7967833afd25f12bd4eaaf6419a6ed3ad544b Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7515 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* AMD Trinity: Update the Trinity SMU FirmwareZheng Bao2014-11-131-1179/+1204
| | | | | | | | | Change-Id: I059047390e80e084f5d7763259d918446d96931e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7294 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan2014-11-091-1/+1
| | | | | | | | Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* AGESA fam15tn fam16kb: Fix missing FCH function prototypesKyösti Mälkki2014-10-222-9/+10
| | | | | | | | | Change-Id: I242664032d368794d828fce73a20f75ded45051d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7151 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* vendorcode/amd/agesa: Use macros already defined in stdlib.hEdward O'Callaghan2014-07-182-35/+3
| | | | | | | | | | | | | We already have these macros define in 'stdlib.h'. Make good use of them here to avoid redefinition conflicts of the pre-processor depending on header inclusion ordering. This has the nice side-effect of syncing up AGESA families in this particular regard. Change-Id: Icf911629a4a1a82b01062fe16af4c8f812b05717 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6199 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* vendorcode/amd/agesa/f15tn: Fix erratum #712Rudolf Marek2014-07-112-1/+54
| | | | | | | | | | | | | | | | | | | | | | | Implement the fix for the erratum #712. - Processor May Hang During Graphics Memory Controller Sequencing The processor may hang during a graphics memory controller (GMC) sleep state transitioning. The failure may be processor specific and may be sensitive to temperature. Potential Effect on System: System hang. Suggested Workaround: BIOS should set D18F2x408_dct[1:0] bit 31 = 1b. See Publication # 48931 Revision: 3.08 Change-Id: I4346fd4ef3cf554ffdaaad5ab6fc84e73532e885 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/6216 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* amd/agesa/f15tn: Invalid inline asm in gcc-intrin.hEdward O'Callaghan2014-06-141-85/+112
| | | | | | | | | | | Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: I87bf101b15bac7c06afa9cec10e2bd4e0cdfd6c7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5941 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* vendorcode/amd/agesa/f*: Fix typo in header guardsEdward O'Callaghan2014-05-221-1/+1
| | | | | | | | | | | | _CPU_L3_FEATIRES_H -> _CPU_L3_FEATURES_H Spotted by Clang Change-Id: I1eabebffc7fd5e4f37b28dabcd28984bed64acd8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5818 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop constructEdward O'Callaghan2014-05-211-3/+3
| | | | | | | | | | | | The semantics of this loop relies on an integer overflow in Index >=0 that implies a return value of (UINT8)-1 which around wraps to 0xFF, or VOLT_UNSUPPORTED. Change-Id: I44d68973d0a80093350b2a8a4d3b46bfbb57917a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5801 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* vendorcode/amd/agesa: Logic typo in GfxPowerPlayLocateTdpEdward O'Callaghan2014-05-191-1/+1
| | | | | | | | | | | | The function GfxPowerPlayLocateTdp() sets MinDeltaSclk to a maximum sentinel value and checks DeltaSclk in a loop to minimize MinDeltaSclk. However, MinDeltaSclk incorrectly self-assigns. Change-Id: Id01c792057681516bba411adec268769a3549aa8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5752 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
* vendorcode/amd: kill some intermediate variables in build systemPatrick Georgi2014-05-191-3/+1
| | | | | | | | | | | They don't exactly add clarity, but increase the risk they're used at some obscure place. Change-Id: Ic74f72dae3f9b7eb2343cb5c51bc44c888e1276c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5787 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* build: move include paths where they belongPatrick Georgi2014-05-191-4/+2
| | | | | | | | | | | | They're _not_ part of the compiler binary, so they have no place in $(CC_*) Change-Id: I1e1c3c0be6f75629450a824ea834e1614d48ed9b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5785 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* agesa: drop non-existing search pathsPatrick Georgi2014-05-191-11/+0
| | | | | | | | | | | | | | With the upcoming CC/CFLAGS/CPPFLAGS split, romcc gets more CPPFLAGS, and it's picky about directories actually existing. Change-Id: Ib9c525296e5be0c8ace935ab8096bc98206cbcc1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5784 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* Introduce stage-specific architecture for corebootFurquan Shaikh2014-05-061-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make all three coreboot stages (bootblock, romstage and ramstage) aware of the architecture specific to that stage i.e. we will have CONFIG_ARCH variables for each of the three stages. This allows us to have an SOC with any combination of architectures and thus every stage can be made to run on a completely different architecture independent of others. Thus, bootblock can have an x86 arch whereas romstage and ramstage can have arm32 and arm64 arch respectively. These stage specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain and compiler flags for every stage. These options can be considered as either arch or modes eg: x86 running in different modes or ARM having different arch types (v4, v7, v8). We have got rid of the original CONFIG_ARCH option completely as every stage can have any architecture of its own. Thus, almost all the components of coreboot are identified as being part of one of the three stages (bootblock, romstage or ramstage). The components which cannot be classified as such e.g. smm, rmodules can have their own compiler toolset which is for now set to *_i386. Hence, all special classes are treated in a similar way and the compiler toolset is defined using create_class_compiler defined in Makefile. In order to meet these requirements, changes have been made to CC, LD, OBJCOPY and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others. Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the toolsets are defined using create_class_compiler. Few additional macros have been introduced to identify the class to be used at various points, e.g.: CC_$(class) derives the $(class) part from the name of the stage being compiled. We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER as they do not make any sense for coreboot as a whole. All these attributes are associated with each of the stages. Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5577 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
* vendorcode/amd/agesa/fam15tn: Build as a static libraryAlexandru Gagniuc2014-04-151-0/+437
| | | | | | | | | | | | | | | | | | | | | Up until now, we were building AGESA by specifying each AGESA source file and adding it to the list of romstage and ramstage source files. As a result, we were compiling each AGESA source twice, despite the fact that it does not depend on the stage we're in. Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. We still keep the practice of specifying every single AGESA directory as an include dir and adding the AGESA CFLAGS to our global CFLAGS; this is needed due to the way AGESA builds. Change-Id: I9b23264129d1c08cb67cabc31d15a68d43ed7624 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5430 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* vendorcode/amd/agesa: Do not hardcode ROM base addressAlexandru Gagniuc2014-04-091-2/+0
| | | | | | | | | | | | | | | | | | | | | | | The ROM address range is set up in the LPC PCI device, register 0x6c. Coreboot already sets that up correctly in the bootblock, however AGESA overrides that to 0xffffff00, which will always map the ROM from 0xff000000. This may conflict with other devices which are assigned address space in that range. If a device is assigned a range between 0xff000000 and the real ROM base, accesses to that device will be diverted to the system ROM, regardless of how other BARs are set up. Since we already need to set up the ROM address range in the bootblock, before calling AGESA, just remove the override from AGESA. Note that not all AGESA versions override this mapping. Change-Id: I592e5d087ed830c9604a04a356912c7654ce56d2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5467 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
* vendorcode/amd/agesa/f*: Improve gcccar.inc assembler compatibility.Edward O'Callaghan2014-03-021-1/+1
| | | | | | | | | | | | A comparison with a two's complement in gcccar.inc has dubious GAS/AT&T notation. Clang miss-parses 0x-1 as an invalid hexadecimal number. Change-Id: I88baa5c2513f062ff309df05916a3832b9bd9bb1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5277 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* AGESA f15tn: Fix GPP ports resumeRudolf Marek2014-02-012-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The AGESA resumes the GPP ports in the romstage using FchInitResetGpp(), which does FchGppPortInitS3Phase() for S3 resume. The PreInitGppLink() looks into CMOS to figure out what ports to just force to Gen1 or Gen2 PCIe. Then boot continues and in the ramstage the rest of GPP init is executed. There is a problem that nobody sets properly the PortDetected flags in the S3 path. As the consequence FchGppDynamicPowerSaving() thinks the GPP port is not enabled and shut downs it. The best fix would be also to remove the CMOS dependency which might be some left over, because AGESA does not use CMOS much for anything else. There could be also some way how to pass the GPP state structure from romstage to ramstage possibly via hudson/resume.c but I don't know how to do that. Similar problem is that the "late" stage of init again "forgets" the PortDetected state. This fix fixes the resume issue on Asus F2A85-M. With this patch applied both GPP ports (used as PCIe x1 and internal ethernet) are working again after resume. Change-Id: Idaf609043abb09441c6790504d66d23e0637588f Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/4671 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* AMD IMC AGESA: Access the data in stack by correct lengthZheng Bao2013-12-051-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bug is hard to find. We were adding the feature of fan control. We met some strange things which could not be explained. Like, sometimes adding printk let the error disappear. Then we traced the code by hardware debug tool (HDT). It turned out the data in stack was overwritten. The values of AccessWidthxx are { AccessWidth8 = 1, AccessWidth16, AccessWidth32,} For the case of AccessWidth8, we only need to access the index/data once. But ReadECmsg and WriteECmsg did the loop twice, 1 more time than they are supposed to do. The data in stack next to "Value" would be overwritten. For all the cases, the code should be OpFlag = OpFlag & 0x7f; switch (OpFlag) { case 1: /* AccessWidth8 */ OpFlag = 0;break; case 2: /* AccessWidth16 */ OpFlag = 1;break; case 3: /* AccessWidth32 */ OpFlag = 3;break; case 4: /* AccessWidth64 */ OpFlag = 7;break; default: error; } Actually, the caller only takes AccessWidth8 as the parameter. We can ignore other cases for now. That is an AGESA bug. AMD's AGESA team own this code. They have given the response that they are going to update this in next release. I presume let them decide the proper way to fix that. Before that, I change the code as little as possible to make it run without crash. Change-Id: I566f74c242ce93f4569eedf69ca07d2fb7fb368d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4297 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
* fam15 vendorcode: Change license to BSD from AMD software licenseSiyuan Wang2013-06-09742-37590/+17556
| | | | | | | | | | | | | fam15 vendorcode (src/vendorcode/amd/agesa/f15tn) was licensed under the AMD software license agreement. Change this license to 3-clause BSD. Change-Id: I7cab09bb58ef7cd24602628e2278672d577214a2 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* AGESA: Add "const" modifier to function parametersBruce Griffith2013-06-066-64/+64
| | | | | | | | | | | | | | Add CONST modifiers to read-only pass-by-reference function parameters in AGESA. This allows the use of "const" modifiers on the declaration of lookup tables that are pass-by-reference. These will be used to identify tables that are copied onto the HEAP but don't need to be. Change-Id: Ie1187a427804fddf47b935a110ad23931a3447a9 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* AMD SATA: Correct »them implement« to »then implement« in commentsPaul Menzel2013-05-032-2/+2
| | | | | | | | | | | | The following command was used to correct all occurences of this typo. $ git grep -l "them implem" | xargs sed -i 's/them implem/then implem/' Change-Id: Iebd4635867d67861aaf4d4d64ca8a67e87833f38 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3145 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in commentsPaul Menzel2013-04-162-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When looking into possible reasons for a proposed revert [1], I noticed that the comments use four arguments for `PCIE_DDI_DATA_INITIALIZER`, but the actual definition only uses three. $ git grep -A1 PCIE_DDI_DATA_INITIALIZER # manually squeeze whitespace in output […] -- src/vendorcode/amd/agesa/f10/AGESA.h:#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ src/vendorcode/amd/agesa/f10/AGESA.h-{mConnectorType, mAuxIndex, mHpdIndex} -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * }, -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * } -- […] So remove the fourth argument in the comments. Luckily the compiler, at least gcc, warns about a wrong number of arguments, and therefore no incorrect code resulted from the wrong documentation. [1] http://review.coreboot.org/#/c/3077/ Change-Id: I3e5a02c66a23af1eb2d86be8dbc7aaa3e5cea05e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* f15tn/Include/OptionIdsInstall.h: Remove idle `… || )`Siyuan Wang2013-03-201-1/+1
| | | | | | | | | | Change-Id: I4aba6cc490ab24c6db345c0c5a64a6a9985ed0ab Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/2864 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* F15tn: Fix all warnings, enable warnings as errorsMartin Roth2013-01-227-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable 'all warnings being treated as errors' in thatcher and parmer. Fixed the following warnings on parmer / thatcher: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c: In function 'GetGlobalCpuFeatureListAddress': src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c: In function 'SaveDeviceContext': src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c: In function 'GetPstateGatherDataAddressAtPost': src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c: In function 'MemNInitNBDataTN': src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32: warning: assignment from incompatible pointer type [enabled by default] src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23: warning: assignment from incompatible pointer type [enabled by default] src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c: In function 'GetGlobalCpuFeatureListAddress': src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c: In function 'SaveDeviceContext': src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0: src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0: warning: "TOP_MEM" redefined [enabled by default] src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0: warning: "TOP_MEM2" redefined [enabled by default] src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0: src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0: warning: "LOCAL_APIC_ADDR" redefined [enabled by default] src/include/cpu/x86/lapic_def.h:9:0: note: this is the location of the previous definition In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0, from src/mainboard/amd/parmer/mainboard.c:28: src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0: warning: "TOP_MEM" redefined [enabled by default] src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0: warning: "TOP_MEM2" redefined [enabled by default] src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2171 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Save and restore F15TN graphics command registerMartin Roth2013-01-211-1/+3
| | | | | | | | | | | | | | | | | In the AGESA routine GfxInitSview() called in the S3save path, the IO Space bit was getting cleared from the command register. This kept seabios from initializing the video bios. If the vbios was loaded by coreboot, this routine was skipped, allowing seabios to initialize vbios as well. I have modified the routine to save and restore the command register instead of clearing the IO Space bit. Change-Id: I756b0606adbc47da96780308c911852e39f547c7 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2172 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
* F15tn / Hudson: Change SATA NumOfPorts register settingMartin Roth2013-01-211-18/+7
| | | | | | | | | | | | | | | | | | | The Number of Ports register says that it should be set to the maximum number of ports supported by the silicon. AGESA was setting this to be the number of enabled ports. If port 1 was the only port with a drive, this value got set to 0, indicating 1 port. This causes SeaBIOS to only look at port 0 and quit, never finding the drive on port 1. Dave Frodin: I also verified that this patch allows a SATA drive plugged into port 2 to be detected without a device in port 1. Change-Id: I5d49e351864449520e3957bbb07edf0f3ec2fd47 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2165 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
* Fix 2 infinite loops if IMC doesn't respondMartin Roth2013-01-101-1/+1
| | | | | | | | | | | | | | | | | | | ACPI code: The ACPI code is not currently being compiled in by default, but assuming that it will be at some point, I'm fixing the loop that waits for the IMC to respond after sending it a command. The loop now exits after 500ms, similar to the function in agesa. Agesa Code: a 16 bit variable will always be less than 100000. Change to be a 32 bit variable. Change-Id: I9430ef900a22d056871b744f3b1511abdfea516e Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2119 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* AMD Hudson: Enable HD audiozbao2012-08-139-91/+499
| | | | | | | | | | | Something about HD audio was scrubbed. Take it back. Change-Id: I0be96fd103f3ebd4e8c7ef09a184b71aa34ee3fd Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1427 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
* AMD Family 15tn: Set the default return value as AGESA_SUCCESS instead of TRUEzbao2012-07-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | The default return value should be AGESA_SUCCESS, which is zero. If it was set as TRUE, the AGESA wrapper would think it was AGESA_UNSUPPORTED. That would make no sense. And it would produce ASSERT warning in AGESA wrapper. On my parmer board, with Engine sample processor, it can not create the correct DMI table. Routine initlate will return AGESS_ERROR. ------Serial message--------- ASSERTION FAILED: file 'src/mainboard/amd/parmer/agesawrapper.c', line 427 DmiTable:100123c3, AcpiPstatein: 10010126, AcpiSrat:0,AcpiSlit:0, Mce:100111ba, Cmc:1001127c,Alib:1001ccd4, AcpiIvrs:0 in agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5 ----------------------------- I believe the processor with acceptable name string will create the right DMI. Change-Id: Ie86955cf9affffc964a7c9f4a2c63077ef2030de Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1350 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* AGESA F15tn: AMD family15 AGESA code for Trinityzbao2012-07-03749-0/+313688
AMD AGESA code for trinity. Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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