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* skylake: Leave SPI controller enabledLee Leahy2015-10-111-5/+0
* skylake: SPI code cleanupLee Leahy2015-10-114-12/+11
* tegra132: increase romstage size for vbootAaron Durbin2015-10-111-2/+2
* vboot: remove remnants of VBOOT_STUBAaron Durbin2015-10-113-3/+0
* intel fsp1_1: prepare for romstage vboot verification splitAaron Durbin2015-10-115-99/+24
* soc/intel/common: remove chipset specific callsAaron Durbin2015-10-116-20/+6
* intel SOC common: Remove unused parametersLee Leahy2015-10-114-10/+8
* Braswell: Modify CB to accomodate new FSPv83Subrata Banik2015-10-113-11/+7
* Skylake: remove the out-dated VR config and un-needed 24mhz calibrationrobbie zhang2015-10-112-121/+0
* skylake: ajdust cache-as-ram region to 64KiBAaron Durbin2015-10-111-1/+1
* intel: update common and FSP cache-as-ram parametersAaron Durbin2015-10-113-14/+31
* Do not show HAVE_MTC on non-tegra210Vladimir Serbinenko2015-10-111-1/+1
* cbfs: add struct cbfsfAaron Durbin2015-10-073-5/+11
* Add EM100 'hyper term' spi console support in ramstage & smmMartin Roth2015-10-054-0/+4
* drivers/uart/Kconfig: Select 8250 mem when 8250 mem32 is enabledAlexandru Gagniuc2015-10-041-1/+0
* tegra124: use the common verstage flowAaron Durbin2015-10-021-12/+3
* broadcom/cygnus: remove verstage.cAaron Durbin2015-10-021-32/+0
* tegra132/tegra210: remove verstage.cAaron Durbin2015-10-012-2/+0
* intel/fsp_baytrail: Remove unused MICROCODE_INCLUDE_PATH from KconfigWerner Zeh2015-10-011-5/+0
* vboot: provide a unified flow for separate verstageAaron Durbin2015-09-304-95/+2
* cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc2015-09-3016-152/+10
* skylake: select HAVE_INTEL_FIRMWAREAaron Durbin2015-09-292-93/+1
* intel: auto include intel/common/firmwareAaron Durbin2015-09-294-4/+0
* skylake: Work around issue in ACPI interpreterDuncan Laurie2015-09-281-2/+12
* skylake: ACPI: Remove Configurable TDP support codeDuncan Laurie2015-09-282-242/+0
* coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin2015-09-244-8/+0
* chromeos: vboot and chromeos dependency removal for sw write protect statePaul Kocialkowski2015-09-233-9/+3
* linking: link bootblock.elf with .data and .bss sections againAaron Durbin2015-09-229-37/+3
* coreboot: introduce commonlibAaron Durbin2015-09-221-1/+1
* broadwell: Switch to using common ACPI _SWS codeDuncan Laurie2015-09-173-64/+15
* braswell: Switch to using common ACPI _SWS codeDuncan Laurie2015-09-175-30/+17
* skylake: Use common ACPI _SWS codeDuncan Laurie2015-09-173-18/+25
* Skylake: update C state latency and power numbersrobbie zhang2015-09-172-18/+27
* t210: lp0_resume: Configure unused SDMMC1/3 pads for low power leakageYen Lin2015-09-171-0/+50
* intel/skylake: Create "RtcLock" Silicon UPD from corebootBarnali Sarkar2015-09-172-0/+4
* intel/common: Add common code for filling out ACPI _SWSDuncan Laurie2015-09-175-0/+167
* Move final Intel chipsets with ME to intel/common/firmwareMartin Roth2015-09-164-225/+9
* fsp1_1: provide binding to UEFI versionAaron Durbin2015-09-1018-114/+14
* intel/skylake: HAVE_UART_MEMORY_MAPPED doesn't exist anymorePatrick Georgi2015-09-101-1/+0
* skylake: Move ACPI init to SOC instead of mainboardDuncan Laurie2015-09-103-7/+17
* intel/common: Print board ID if enabledDuncan Laurie2015-09-101-0/+8
* skylake: Enable DPTF based on devicetree settingDuncan Laurie2015-09-102-0/+9
* Skylake: Print GPIO MMIO base and pad config using gpio_debug tokenSubrata Banik2015-09-101-0/+6
* skylake: dptf: Add TSR3 thermal sensor and CPU code cleanupDuncan Laurie2015-09-092-6/+71
* braswell: acpi: Allow DPTF thresholds to be defined at board-levelShawn Nematbakhsh2015-09-092-25/+49
* intel/skylake: ACPI: Clean up formatting in and fix ASL codeDuncan Laurie2015-09-094-296/+216
* verstage: use common program.ld for linkingAaron Durbin2015-09-099-9/+0
* x86: bootblock: remove linking and program flow from build systemAaron Durbin2015-09-0912-8/+16
* rk3288: Allow board-specific APLL (CPU clock) settingsDavid Hendricks2015-09-082-5/+16
* skylake: igd: clean up igd.cDuncan Laurie2015-09-081-15/+9
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