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* linking: link bootblock.elf with .data and .bss sections againAaron Durbin2015-09-229-37/+3
* coreboot: introduce commonlibAaron Durbin2015-09-221-1/+1
* broadwell: Switch to using common ACPI _SWS codeDuncan Laurie2015-09-173-64/+15
* braswell: Switch to using common ACPI _SWS codeDuncan Laurie2015-09-175-30/+17
* skylake: Use common ACPI _SWS codeDuncan Laurie2015-09-173-18/+25
* Skylake: update C state latency and power numbersrobbie zhang2015-09-172-18/+27
* t210: lp0_resume: Configure unused SDMMC1/3 pads for low power leakageYen Lin2015-09-171-0/+50
* intel/skylake: Create "RtcLock" Silicon UPD from corebootBarnali Sarkar2015-09-172-0/+4
* intel/common: Add common code for filling out ACPI _SWSDuncan Laurie2015-09-175-0/+167
* Move final Intel chipsets with ME to intel/common/firmwareMartin Roth2015-09-164-225/+9
* fsp1_1: provide binding to UEFI versionAaron Durbin2015-09-1018-114/+14
* intel/skylake: HAVE_UART_MEMORY_MAPPED doesn't exist anymorePatrick Georgi2015-09-101-1/+0
* skylake: Move ACPI init to SOC instead of mainboardDuncan Laurie2015-09-103-7/+17
* intel/common: Print board ID if enabledDuncan Laurie2015-09-101-0/+8
* skylake: Enable DPTF based on devicetree settingDuncan Laurie2015-09-102-0/+9
* Skylake: Print GPIO MMIO base and pad config using gpio_debug tokenSubrata Banik2015-09-101-0/+6
* skylake: dptf: Add TSR3 thermal sensor and CPU code cleanupDuncan Laurie2015-09-092-6/+71
* braswell: acpi: Allow DPTF thresholds to be defined at board-levelShawn Nematbakhsh2015-09-092-25/+49
* intel/skylake: ACPI: Clean up formatting in and fix ASL codeDuncan Laurie2015-09-094-296/+216
* verstage: use common program.ld for linkingAaron Durbin2015-09-099-9/+0
* x86: bootblock: remove linking and program flow from build systemAaron Durbin2015-09-0912-8/+16
* rk3288: Allow board-specific APLL (CPU clock) settingsDavid Hendricks2015-09-082-5/+16
* skylake: igd: clean up igd.cDuncan Laurie2015-09-081-15/+9
* braswell: Tristate CFIO 139 and CFIO 140Ravi Sarawadi2015-09-082-0/+8
* Skylake:Set DISB inside romstage after mrc initDhaval Sharma2015-09-082-2/+17
* skylake: Clean up chip.hDuncan Laurie2015-09-081-26/+7
* skylake: Apply USB2 and USB3 port enable/disable settingsDuncan Laurie2015-09-081-11/+9
* skylake: Remove dead codeLee Leahy2015-09-082-21/+0
* skylake: refactor flash_controller codeAaron Durbin2015-09-082-208/+158
* skylake: move flash_controller.h to the proper placeAaron Durbin2015-09-083-5/+5
* skylake: fix eventlog on resume pathAaron Durbin2015-09-081-0/+12
* skylake: allow timer_monotonic_get() in all stagesAaron Durbin2015-09-082-25/+3
* skylake: ACPI: Clean up GPIO controllerDuncan Laurie2015-09-081-37/+27
* skylake: ACPI: Clean up and fix XHCI ACPI DeviceDuncan Laurie2015-09-083-252/+165
* skylake: ACPI: Remove SerialIO ACPI mode codeDuncan Laurie2015-09-084-600/+20
* skylake: ACPI: Move storage controllers to separate fileDuncan Laurie2015-09-083-29/+127
* skylake: ACPI: Remove itss.asl and cleanup irqlinks.aslDuncan Laurie2015-09-083-297/+137
* skylake: iomap: Remove unused RCBA regionDuncan Laurie2015-09-081-5/+1
* skylake: PCR: Add Port ID for SCSDuncan Laurie2015-09-081-2/+3
* skylake: ACPI: Add functions for PCR accessDuncan Laurie2015-09-082-0/+77
* skylake: ACPI: Clean up pch.aslDuncan Laurie2015-09-085-30/+28
* skylake: ACPI: Fix and clean up PCIE _PRT entriesDuncan Laurie2015-09-083-88/+156
* microcode: Unify rules to add microcode to CBFS once againAlexandru Gagniuc2015-09-072-22/+0
* Drop "See file CREDITS..." commentStefan Reinauer2015-09-0710-30/+0
* bootstate: remove need for #ifdef ENV_RAMSTAGEAaron Durbin2015-09-044-25/+2
* x86: remove cpu_incs as romstage Make variableAaron Durbin2015-09-042-3/+3
* bootmode: add display_init_required()Aaron Durbin2015-09-044-20/+22
* soc/intel: Fix dependency of CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEMAlexandru Gagniuc2015-08-313-3/+3
* imgtec/pistachio: remove timestamp_get() implementationAaron Durbin2015-08-311-6/+1
* soc/intel/braswell/Kconfig: Remove ENABLE_MRC_CACHE KconfigAlexandru Gagniuc2015-08-311-1/+0
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