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* Correct spelling of "spacing" (in comments).Jonathan Kollasch2010-10-191-2/+2
* Revision 5966 changed the end of line style of the 3 modified files. This cha...Scott Duplichan2010-10-191-1202/+1202
* When debug logging is enabled, a message such as '* AP 02 timed out:02010501'Scott Duplichan2010-10-191-1192/+1202
* Remove various .c #includes from Intel i810/i82801ax/i82801bx boards.Uwe Hermann2010-10-135-5/+29
* Convert all Intel i810 boards to CAR.Uwe Hermann2010-10-132-1/+7
* Trivial. Clean up code and add some comments.Zheng Bao2010-10-132-39/+42
* Move translate_spd_to_i82810[] from .h to .c file (trivial).Uwe Hermann2010-10-122-57/+54
* We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.Uwe Hermann2010-10-122-5/+1
* Factor out a few commonly duplicated functions from northbridge.c.Uwe Hermann2010-10-1121-768/+7
* Remove various .c #includes from Intel 440BX/82371EB boards.Uwe Hermann2010-10-094-4/+21
* Trivial. Spell checking.Zheng Bao2010-10-097-44/+37
* Trivial. Spell checking.Zheng Bao2010-10-096-13/+13
* Trivial. Spell checking.Zheng Bao2010-10-084-18/+18
* Trivial. Fix the typo.Zheng Bao2010-10-082-4/+4
* Remove duplicate line from pci_ids.h.Jonathan Kollasch2010-10-077-49/+31
* Convert all Intel 440BX boards to Cache-as-RAM (CAR).Uwe Hermann2010-10-061-1/+2
* Use %p instead of %x to print void *.Jonathan Kollasch2010-10-051-1/+1
* Remove lib/ramtest.c-include from all CAR boards.Patrick Georgi2010-10-058-8/+57
* Fix spelling/typos in comments.Jonathan Kollasch2010-10-021-8/+8
* Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,Patrick Georgi2010-10-015-7/+4
* Make i945/raminit.c:fsbclk() return u16 rather than intPeter Stuge2010-10-011-5/+5
* Split NORTHBRIDGE_INTEL_I945 into more precise _I945GC and _I945GMPeter Stuge2010-10-013-33/+20
* Move several i945 config #defines from romstage.c to Kconfig.Patrick Georgi2010-10-012-17/+51
* Trivial. Re-indent the code.Zheng Bao2010-10-016-16/+16
* Rename build system variables to be more intuitive, andPatrick Georgi2010-09-3021-67/+67
* Trivial. re-Indent the code.Zheng Bao2010-09-282-35/+35
* Obviously missing brackets.Xavi Drudis Ferran2010-09-272-4/+5
* Mark read-only data as read-only, so the global vars test doesn't fail on it.Patrick Georgi2010-09-253-4/+4
* Various CONFIG_DEBUG_RAM_SETUP related fixes (trivial).Uwe Hermann2010-09-254-5/+7
* Keep the mc146818rtc.h include close to the option table include whereMyles Watson2010-09-252-1/+3
* - Fix race condition in option_table.h generation by moving the includeStefan Reinauer2010-09-255-5/+24
* Complete the code which was missing.Zheng Bao2010-09-211-0/+3
* Fix the typo. Field DisAutoRefresh is in DramTimngHi.Zheng Bao2010-09-211-1/+1
* A number of cleanups for 440BX raminit code.Keith Hui2010-09-201-30/+42
* Add reserved areas for fam10.Myles Watson2010-09-131-1/+18
* Port k8 UMA handling to fam10.Myles Watson2010-09-131-0/+11
* Fix a typo reported by Sylvain Hitier.Myles Watson2010-09-131-1/+1
* Convert i945 boards to use reserved resources instead of directly addingMyles Watson2010-09-131-9/+17
* Move memory type information out of some AMD sockets.Myles Watson2010-09-102-0/+72
* Please find appended. This patch gets rid of the %gs magic altogether,Arne Georg Gleditsch2010-09-094-6/+37
* Also improve boot time on AMD for the DDR3 code path.Arne Georg Gleditsch2010-09-092-2/+2
* Apparently, it's not crucial to clear this at the exact moment we switchArne Georg Gleditsch2010-09-091-1/+1
* Trivial. Currently the max frequency is preset as 400Mhz. We need to set aZheng Bao2010-09-051-0/+1
* AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.Kerry She2010-09-042-2/+4
* Trivial warning fix for adl855pc.Myles Watson2010-09-021-0/+4
* Get Byte65/66 for register manufacture ID code. RegMan1Present willZheng Bao2010-08-311-1/+9
* We call this cache as ram everywhere, so let's call it the same in KconfigStefan Reinauer2010-08-302-17/+17
* This file was missing from r5751.Andreas Schultz2010-08-301-0/+76
* Rework i855GM/i855GME supportAndreas Schultz2010-08-304-175/+926
* Multi-DIMMS on AMD ddr2 MCT channel B fixed.Kerry She2010-08-301-2/+2
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