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path: root/src/northbridge/amd/amdmct
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* Use the coreboot pci config read/write functions instead of direct cf8/cfcMarc Jones2009-09-141-11/+2
* Without this patch, if we only got a DIMM in Channel B, memory can not beZheng Bao2009-08-251-3/+3
* This patch is about the DA-C2 and RB-C2. Chip with install processorZheng Bao2009-08-242-1/+2
* The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instea...Zheng Bao2009-08-191-14/+14
* This is an obvious bug which I overlooked when I worked on the AM2r2Zheng Bao2009-07-171-2/+2
* Add AMD family 10 AM2r2 support.Zheng Bao2009-07-012-32/+33
* Fix for Erratum 350 for AMD Fam10h CPUs.Marco Schmidt2009-06-062-3/+71
* Update equivalent processor revision ID to load latest microcode patches andMarc Jones2009-05-141-0/+3
* Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de>Stefan Reinauer2008-12-052-1/+6
* Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).Marc Jones2008-07-232-18/+25
* Remove inline from FAM10 CPU initialization functions.Marc Jones2008-04-252-4/+4
* Add early MSR and PCI register initialization. Marc Jones2008-04-221-16/+68
* Bring Fam10 memory controller init up to date with the latest AMD BKDGMarc Jones (marc.jones2008-04-118-145/+265
* Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer2008-01-181-2/+2
* Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer2008-01-1823-23/+23
* Initial AMD Barcelona support for rev Bx.Marc Jones2007-12-1923-0/+10943
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