summaryrefslogtreecommitdiffstats
path: root/src/mainboard/intel
Commit message (Collapse)AuthorAgeFilesLines
* i945: Consolidate FADT codeclassic-2014.10Vladimir Serbinenko2014-10-181-129/+2
| | | | | | | | Change-Id: I076cba7d21926cabf90d485de50268ae40c435f3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7087 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* bd82x6x: Consolidate common GNVS initVladimir Serbinenko2014-10-171-9/+0
| | | | | | | | Change-Id: Iea035f80695623e4e8d53eea7e3ec294d868fb5b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7053 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Add board_info for all Google/Intel boards mitting the fileStefan Reinauer2014-10-172-0/+6
| | | | | | | | | Change-Id: Iac53462ab3621d96ba15e2fde2800212584246db Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7072 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
* xe7501devkit: Kill unused cmos.layoutVladimir Serbinenko2014-10-171-52/+0
| | | | | | | | Change-Id: I04b485945a1830deaf5a695507ea81809edbceeb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7073 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
* bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.Vladimir Serbinenko2014-10-161-20/+1
| | | | | | | | Change-Id: I9ba1fa5f9ad38cb619466c6199eacd219bc53281 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6921 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* sandybridge: Move common northbridge finalize to northbridge code.Vladimir Serbinenko2014-10-161-21/+3
| | | | | | | | Change-Id: I6d4178e5aaffc1330b0953b0601bf6b448250a8e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6920 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* i945: Convert to per-device ACPIVladimir Serbinenko2014-10-151-149/+1
| | | | | | | | Change-Id: Iee3ee33ca58b8c722d2d38aae31e7130032512ad Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* intel/fsp_baytrail: Fix SMM/SMIKayalvizhi Dhandapani2014-10-091-1/+1
| | | | | | | | | | | | | | | | | With SMM enabled the boot stopped while patching up global NVS in DSDT. The cause is that both CPUs are assigned the same SMBASE address. So update the "cpu_smm_do_relocation()" function so that each CPU gets a different SMBASE address Based on rmodule work that wasn't propagated to the FSP version: commit 3eb8eb7eba55cdfd64c8d50181ea066526ff6485 Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7026 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
* intel/minnowmax: Enable S3 suspend/resumeMohan D'Costa2014-09-291-0/+1
| | | | | | | | | | | | | | This enables S3 Suspend / Resume support for MinnowMax board using Intel's Bay Trail FSP Tested resume from Power Button and Magic Packet. Change-Id: I021122a68c05f2e725cabb8f3946249afe802bbe Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp> Reviewed-on: http://review.coreboot.org/6972 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
* google/link, intel/wtm2: Do not include non-existent "hda.h" in i915.cPaul Menzel2014-09-221-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 75c83870 (azalia: Shrink boilerplate) [1] removed the header file `hda_verb.h`. This header is still included in the mainboard’s `i915.c`, causing the following build error, when native graphics initialization is enabled. CC mainboard/intel/wtm2/i915.ramstage.o src/mainboard/intel/wtm2/i915.c:34:22: fatal error: hda_verb.h: No such file or directory This was not caught, as native graphics initialization is not enabled for the build tests. It turns out that the array `mainboard_cim_verb_data` is not used in `src/mainboard/intel/wtm2/hda_verb.h`, so fix the problem by removing the inclusion. [1] http://review.coreboot.org/6840 Change-Id: Ic902581c6809a1069e169cc874678146a24d75f3 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6945 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
* haswell: Move to per-device ACPIVladimir Serbinenko2014-09-222-327/+2
| | | | | | | | Change-Id: Ic724dcf516d9cb78e89698da603151a32d24e978 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6814 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* azalia: Shrink boilerplateVladimir Serbinenko2014-09-139-40/+32
| | | | | | | | | Change-Id: Ib3e09644c0ee71aacb067adaa85653d151b52078 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* payloads/external/SeaBIOS: Allow setting buffers below 0xC0000Martin Roth2014-09-121-0/+8
| | | | | | | | | | | | | | | | | | | | Add the option to coreboot to set the SeaBIOS buffers below 0xC0000. This is a requirement on the Intel Rangeley processor because it is designed so that only the processor can write the higher memory areas. This prevents USB and SATA from bus-mastering into the buffers when they're set in the typical 0xE0000 area. This will be set to Y unless defaulted to N by the mainboard or chipset. Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak Change-Id: I15638605d1c66a2277d4b852796db89978551a34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* Move nehalem/sandy/ivy to per-device acpiVladimir Serbinenko2014-09-111-155/+1
| | | | | | | | Change-Id: I3d664ab575bf9c49a7bff9a395fbab96748430d0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6802 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
* Consolidate intel vga int15 hooksVladimir Serbinenko2014-09-058-394/+12
| | | | | | | | Change-Id: I9366dded98bf15f6da44ce893dd10698ba09fd55 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6820 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* azalia: Use convenience macros throughoutVladimir Serbinenko2014-09-058-152/+41
| | | | | | | | Change-Id: Ic044bf155bfcf93fa7cf3afd7287b7d0b615ef6d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Remove dead video.aslVladimir Serbinenko2014-08-227-146/+0
| | | | | | | | Change-Id: Iadaa6172347ebb7d367d1faa6ed9462fff07d7e6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6730 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* azalia: Move shared variable to separate fileVladimir Serbinenko2014-08-184-12/+4
| | | | | | | | | Change-Id: Icf46ad1397c67478887c80a627b8f4eb0a67e542 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6695 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mainboard/intel/mohonpeak: code cleanupMartin Roth2014-08-185-37/+12
| | | | | | | | | | | | | | | Code cleanup requested in commit 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" - Change com2 to COM2 in Kconfig text - clean up includes of headers - fix whitespace Change-Id: I828bc4781ee7de95be5546206c5d6033b75293d9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6607 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* southbridge/intel/fsp_rangeley: fix to include irqroute.h twiceMartin Roth2014-08-181-0/+5
| | | | | | | | | | | | | | | | This matches what was done on baytrail in commit bfca984b - soc/intel/fsp_baytrail: set up for including irqroute.h twice irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Change-Id: I709f9370ce7db1b3ffac2297aeaba5cc670ec20c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* mainboard/XXX/YYY/dsdt.asl: Whitespace fixMartin Roth2014-08-182-2/+2
| | | | | | | | | | | | | Use tab between "COREBOOT", and comment. This fix was requested in 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" Change-Id: If9fb6158cca95341ab57db1125e85648b616b72c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6601 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* intel/cpu: rename car.h to romstage.hAaron Durbin2014-08-158-8/+8
| | | | | | | | | | | | | This header has nothing to do with cache-as-ram. Therefore, 'car' is the wrong term to use. It is about providing a prototype for *romstage*. Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6661 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Intel: Add common header file for CAR setupEdward O'Callaghan2014-08-148-0/+8
| | | | | | | | | | | | | | | | | | | | | | When passing '-ffreestanding' the 'main' romstage.c may no longer necessarily be considered the entry point. From the C specification in 5.1.2.1 Freestanding environment; "In a freestanding environment (in which C program execution may take place without any benefit of an operating system), the name and type of the function called at program startup are implementation-defined." Clang complains about these being missing as Clang is somewhat more strict about the spec than GNU/GCC is. An advantage here is that a different entry-point type-signature shall now be warned about at compile time. Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* mainboard/intel/minnowmax: clean up includes & whitespaceMartin Roth2014-08-121-22/+0
| | | | | | | | | | | Clean up as requested in commit e6df041b. No functional changes. Change-Id: Iec3f7ee25fd8351c7e13d660e2df6461f7745478 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6597 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* bayleybay_fsp: Add bakersport board variantMartin Roth2014-08-114-0/+115
| | | | | | | | | | | | | | | | | | | | The Bakersport board is a variant of the Bayley Bay mainboard that uses one ECC DIMM instead of two non-ECC dimms. This commit uses the Bayley Bay mainboard directory and modifies the required pieces to add the Bakersport board variant. It disables the second DIMM, points to an ECC version of the FSP, and sets the board name to be Bakersport instead of Bayley Bay. All of the code is still contained in the bayleybay_fsp directory. It seems like duplicating the whole directory for the one line of code that's actually different between the two platforms. Change-Id: Ia31e9ee927a6810a01a1ae143fcb00cfb7d8a7aa Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5983 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* mainboard/intel/minnowmax: Add MinnowMax mainboardMartin Roth2014-08-1117-0/+1232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MinnowMax board using Intel's Bay Trail FSP Working: - Booting from SATA / USB / (USB3 with latest SeaBIOS) Not working: - Boot from SD - S3 Suspend / Resume ***** To configure the FSP ***** Download the Bay Trail FSP and the binary config tool: Modify the standard Bay Trail FSP: run the bct tool with the command line options: bct --bin <Bay Trail FSP Binary> \ --absf src/vendorcode/intel/fsp/baytrail/absf/minnowmax_Xgb.absf \ --bout <path to save the updated FSP to> Here are the required changes for modifying the FSP manually: Enable Memory Down: Enabled DRAM Speed: 1066 MHz DIMM_DWidth: x16 DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max) tCL: 7 tRP_tRCD: 7 tWR: 8 tRRD: 6 tRTP: 4 tFAW: 27 Other FSP values can remain the same. ***** To configure the vbios ***** The vbios is in the Bay Trail FSP package. Download Intel's "Binary Modification Program" (BMP) Use it to disable all ports except HDMI on port B. Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6429 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* soc/intel/fsp_baytrail: set up for including irqroute.h twiceMartin Roth2014-08-111-0/+5
| | | | | | | | | | | | | | irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Add a time. Change-Id: I882cbbff0f73bdb170bd0f1053767893722dc60a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6572 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* intel/eagleheights/Kconfig: Do not set twice MMCONF_BASE_ADDRESSDaniele Forsi2014-08-091-4/+0
| | | | | | | | | | | | | Remove the lines added in an apparently unrelated commit 53ad9f58 (Make CONFIG_HAVE_HIGH_TABLES consistent in where and how it is set.) which touched the symbol HAVE_HIGH_TABLES in all files except this one and keep those added the same day in commit 6842c029 (Remove MAINBOARD_OPTIONS, which is a relic from early kconfig development.) Change-Id: Ib055c25a0a0795a50a36e65218c8f31e921f1502 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6417 Tested-by: build bot (Jenkins) Reviewed-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* sandy/ivybridge: Make UMA size configurable.Vladimir Serbinenko2014-08-031-1/+13
| | | | | | | | | Change-Id: I9aa3652d1b92cece01d024e19bdc065797896001 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6470 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000Martin Roth2014-07-3021-0/+1296
| | | | | | | | | | | | Add the Mohon Peak CRB. Updates to come. Change-Id: I0a8496d502bab905c6f35eff9fcd7eda266831ed Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/6371 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* mainboard: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-189-17/+0
| | | | | | | | | Change-Id: If29a70be4fb56ebb0dbf6d510412cbe2f34480ef Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6291 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* src/superio/smsc/lpc47m15x: Avoid #include early_serial.cEdward O'Callaghan2014-07-181-32/+6
| | | | | | | | | | | | | Provide proper header and function type-signatures for Super I/O romstage component. Fix mainboard's bogous romstage component to match. Change-Id: Icd02199690d0c428b2daadf702d50714dc367692 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5924 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* mainboard,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-1723-24/+0
| | | | | | | | Change-Id: Ib531a54db7df6b49a6218f689dcaab712e9dfb01 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6292 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* mainboard: Trivial - drop trailing blank lines at EOF in .hEdward O'Callaghan2014-07-084-4/+0
| | | | | | | | Change-Id: I4a4ee99468e5f1dae8412ae565a34290493db726 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6201 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
* mainboard: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-0819-21/+0
| | | | | | | | Change-Id: I05d6d22664155ac8478e665733f816776e277c22 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6200 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* Intel Lynx Point boards: Kconfig: Add `HAVE_ME_BIN`Paul Menzel2014-07-052-0/+8
| | | | | | | | Change-Id: Ib7d2a5c14675427fe9556a6b81ed5397f17937d8 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6049 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Intel Lynx Point boards: Kconfig: Add `HAVE_IFD_BIN`Paul Menzel2014-07-052-0/+8
| | | | | | | | Change-Id: I0ea09d75cb05687407fb152642578e19824d1c4c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6048 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* intel: Make monotonic timer a first class citizenEdward O'Callaghan2014-07-052-1/+2
| | | | | | | | | | | | | The monotonic time now needs to be a first class citizen in Coreboot as it is a hard dependency of the drivers/spi flash command polling function. Change-Id: I4e43d2680bf84bc525138f71c2b813b0f6be5265 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6135 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* bayleybay_fsp: Switch from EHCI controller to XHCIMartin Roth2014-06-261-2/+2
| | | | | | | | | | | | | | | | - Disable the EHCI controller and enable the XHCI controller. SeaBIOS has been tested on the board and boots an OS from a flashdrive at SuperSpeed. This also enables the top USB port on the 2-port stack, which goes through a High Speed Inter-Chip port. The HSIC port is only enabled through the XHCI device. Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6106 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
* i945 boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki2014-06-251-1/+0
| | | | | | | | Change-Id: I1bbcba086f841a90544b827ae807a3c351d19d21 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6036 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
* sandy/ivy boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki2014-06-251-1/+0
| | | | | | | | | | | Like with other more recent boards already using DYNAMIC_CBMEM, the pointer to TOC is no longer stored in GNVS for ACPI. Change-Id: If2e11294202c40793ec985e2c0c006bbfcd03d3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6034 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
* i945 boards: Drop disabled ram_check() callsKyösti Mälkki2014-06-251-17/+0
| | | | | | | | | | | | | | | | This code would not get enabled just by flipping the options in menuconfig, also ramcheck() no longer test the range like the parameters would imply. We should add non-destructive ram_check() on S3 resume path to verify memory controller configuration has been properly recovered. Change-Id: Ie4675c4770146c4312cdfbc81afa19f243f90ee4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6027 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* bayleybay_fsp: Add comments for the MMC/SD devices in devicetreeMartin Roth2014-06-231-4/+4
| | | | | | | | | | | | | | | This just adds some additional comments for the EMMC / SD / SDIO PCI devices in devicetree. The documentation states that the EMMC 4.1 device shouldn't be used, but it's available to enable in the FSP. Because it can be enabled, I've included it in the devicetree even though its use is discouraged. Change-Id: I64633fe1908368f69a8d4031aa900b0bceb2189e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6089 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Remove guarding #includes by CONFIG_FOO combinationsEdward O'Callaghan2014-06-211-2/+0
| | | | | | | | | | | | | | First of many to remove guarding the inclusion of headers based on CONFIG_ options. This *potentially* could hide issues such as functions being swapped from under our feet, since different runtime behaviour could be declared with the function same name and type-signature. Hence, depending on the header we happen to get may change runtime behaviour. Change-Id: Ife56801c783c44e1882abef711e09b85b7f295a4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6055 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* intel boards: Use acpi_is_wakeup_s3()Kyösti Mälkki2014-06-211-1/+1
| | | | | | | | | Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6071 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* sandy/ivy boards: Use acpi_s3_resume_allowed()Kyösti Mälkki2014-06-201-10/+11
| | | | | | | | | Change-Id: I8e0d43293e095c1c76c3cfef1f426737624ea37f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6063 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* intel/i945 gm45: Use acpi_s3_resume_allowed()Kyösti Mälkki2014-06-201-10/+11
| | | | | | | | | Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6061 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* intel/bayleybay_fsp: Drop redundant EARLY_CBMEM_INITKyösti Mälkki2014-06-181-1/+0
| | | | | | | | | | | | This is implied from DYNAMIC_CBMEM from soc/. Change-Id: I8cd8c2dff723950377998750377a3168f1f5fc5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6029 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
* mainboard: Clear up remaining SIO_PORT from KconfigEdward O'Callaghan2014-06-182-6/+4
| | | | | | | | | | | Push back any board specific values back into romstage.c #defines and drop any remaining fragments of CONFIG_SIO_PORT in-tree. Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6045 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki2014-06-185-15/+0
| | | | | | | | | | This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM. Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6032 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
OpenPOWER on IntegriCloud