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* i915_reg: Declare LVDS register values.Vladimir Serbinenko2014-06-011-0/+5
| | | | | | | | Change-Id: If8b3578c4fa31bf9f09c0053a5cac7ebc993b634 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5319 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* drivers/intel/fsp: update enable_mrc_cache with fast bootMartin Roth2014-05-291-1/+2
| | | | | | | | | | | | | When going from a configuration with fast boot disabled to one with it enabled, ENABLE_MRC_CACHE was not being enabled properly. This forces it on with ENABLE_FSP_FAST_BOOT. Change-Id: If7b6374e0c0a1d5403a50a1b0a958cea6f96cc88 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/5794 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* add rtc_init() to romstageMartin Roth2014-05-292-1/+4
| | | | | | | | | | | | | The FSP clears the bit that tells us whether or not the RTC has lost power when it sets up memory. Because of this, we need to initialize the RTC in romstage instead of ramstage. Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5735 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* lenovo: Add lenovo_mainboard_partnumber.Vladimir Serbinenko2014-05-252-1/+8
| | | | | | | | Change-Id: Ie10dcb742fe0884dd94ff5960e2e4b116f633243 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5246 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* drivers/pc80/Kconfig: Revert PS/2 initialization defaultsPatrick Georgi2014-05-231-1/+0
| | | | | | | | | | | | | Remove the inconsistent behaviour based on unrelated configuration: PS/2 init is now always enabled. This can change once we find a better approach. Change-Id: Ia8d55032f0e5eca0bf82d77df7dab95bcb2b353a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5634 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Peter Stuge <peter@stuge.se>
* drivers: Drop GbE stub driversEdward O'Callaghan2014-05-205-77/+0
| | | | | | | | | | | | | | | | These NIC stub drivers were to initialize the Gigabit Ethernet adapters just enough to keep coreboot from trying to execute an option ROM. However this is no longer required as non-VGA option roms are not ran; See: b32816e Remove PCI_ROM_RUN option Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5777 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* drivers/spi/sst.c: Remove unused func to_sst_spi_flash()Edward O'Callaghan2014-05-181-5/+0
| | | | | | | | | | | Trips up clang builds with a warn treated as error. Change-Id: I9c0e2930ba8a60c7ad6063e9826b1b8638185505 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* build: separate CPPFLAGS from CFLAGSPatrick Georgi2014-05-171-1/+1
| | | | | | | | | | | There are a couple of places where CPPFLAGS are pasted into CFLAGS, eliminate them. Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5765 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* build: CPPFLAGS is more common than INCLUDESPatrick Georgi2014-05-171-1/+1
| | | | | | | | | | | Rename INCLUDES to CPPFLAGS since the latter is more commonly used for preprocessor options. Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5764 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* drivers/pc80/Kconfig: simplify PS/2 selection rulesPatrick Georgi2014-05-151-1/+1
| | | | | | | | | | | | There's no need to state the dependency twice. Change-Id: Ia241d441211c6f476d0a6ed7589b038f7a220265 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5633 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* src/drivers/pc80: Remove empty struct keyboardEdward O'Callaghan2014-05-131-1/+1
| | | | | | | | | | | | | | This is a empty struct that has propagated through the superio's & ec's but really does nothing. Time to get rid of it before it adds yet more cruft. However, since this touches many superio's at once we do this in stages by first changing the function type to be a pure procedure. Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5617 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
* Intel FSP: add a shared set of functions for the FSPMartin Roth2014-05-097-0/+1141
| | | | | | | | | | | | | | - Move the non chipset-specific fsp pieces out of the chipset into a shared area. This is used by northbridge / southbrige / SOC code. It pulls in pieces from Kconfig, Makefile and FSP specific code. - Enabled in the CPU code with a Kconfig "select PLATFORM_USES_FSP" Change-Id: I7ffa934c1df09b71d48a876a56e3b888685870b8 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5635 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* drivers/pc80/Kconfig: Do not init PS/2 keyboard if GRUB 2 is chosen as payloadPaul Menzel2014-05-021-2/+2
| | | | | | | | | | | If the user selects GRUB 2 as the payload in Kconfig, coreboot does not need to initialize the PS/2 keyboard as GRUB 2 is going to do it. Change-Id: Ia5d902e7c0fa34eaff26a31507751815bf2d2581 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5583 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* drivers/pc80/Kconfig: Do not init PS/2 keyboard if SeaBIOS is chosen as payloadPaul Menzel2014-05-021-1/+2
| | | | | | | | | | | | | | | | | | | | As the Kconfig description of `DRIVERS_PS2_KEYBOARD` says, SeaBIOS is able to initialize the PS/2 keyboard itself, so it is not necessary to let coreboot do it. SeaBIOS is also able to do it faster as discussed in a thread on the coreboot mailing list from October 2010 [1]. In that thread it was also proposed to not let coreboot initialize the PS/2 coreboot when SeaBIOS is used as a payload. [1] http://www.coreboot.org/pipermail/coreboot/2010-October/thread.html#61310 subject: [coreboot] coreboot+seabios timings Change-Id: I1248cec3e2ca5b9311e46df8aabf67e14ffd4ea6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* drivers/pc80/Kconfig: Mention that GRUB 2 is able to init PS/2 keyboardPaul Menzel2014-05-021-1/+1
| | | | | | | | Change-Id: I0783ee123e0e1ecd5603bc6a40b53d3b0c23bf6d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* console: Drop EARLY_CONSOLE optionKyösti Mälkki2014-04-302-2/+2
| | | | | | | | | | | | | | | We have means to easily disable a specific console in romstage if necessary, so this global option makes little sense. The option was initially introduced as a work-around for build issues around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs. Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5607 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* uart: Support multiple portsKyösti Mälkki2014-04-304-34/+29
| | | | | | | | | | | | | | | | The port for console remains to be a compile time constant. The Kconfig option is changed to select an UART port with index to avoid putting map of UART base addresses in Kconfigs. With this change it is possible to have other than debug console on different UART port. Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5342 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* SPI: Use common dependency in KconfigKyösti Mälkki2014-04-291-11/+5
| | | | | | | | | | Change-Id: I11118a4fe1e05017349feae004f98a17bb02386b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5605 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* uart8250io: Fix build with DEBUG_SMIKyösti Mälkki2014-04-261-1/+2
| | | | | | | | Change-Id: I5110af348d22c0abc940f0922854fdd7e0c7e2e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* Get rid of HAVE_INIT_TIMER config optionFurquan Shaikh2014-04-261-0/+4
| | | | | | | | | | | | | | | There is redundancy in terms of use of init_timer. We have a Kconfig option to decide whether a board has init_timer as well as we use a stub for init_timer in places where we do not have any init_timer defined. Thus, remove the Kconfig option. Henceforth, all boards that do not have init_timer functionality can include a stub_timer if required. Change-Id: I35d38ec686f4dc92861cf9248f9b540323cd98ae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5569 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* usbdebug: Add BeagleBone BlackKyösti Mälkki2014-04-221-0/+5
| | | | | | | | | | | Avoid some confusion as the selection of "BeagleBone" is not compatible with the product "BeagleBone Black". Change-Id: If73f80565cd26d2b41db972b4474ab85b609c1ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4289 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* Drop drivers/generic/debugKyösti Mälkki2014-04-225-294/+0
| | | | | | | | | | Not very popular nor useful nowadays. Change-Id: I3dc0f7aaf188950a43f5350d3a95669fbbdcfd94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4554 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* console: Drop driver list in ramstageKyösti Mälkki2014-04-182-13/+0
| | | | | | | | | | | | | | | | | | This framework was only available in ramstage. So we had to define console output functions separately for bootblock, romstage and SMM. Follow-up patches will re-enable all the consoles removed here, in a more flexible fashion, and with less lines-of-code and copy-paste. Also the driver list is not in a well-defined order and some of the loops could exit without visiting all drivers. NOTE: This build has no console in ramstage. Change-Id: Iaddc495aaca37e2a6c2c3f802a0dba27bf227a3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5337 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* OxPCIe uart: Move under drivers/uartKyösti Mälkki2014-04-0910-18/+16
| | | | | | | | | | | This driver is only a thin shell for uart8250mem and we could extend it with further compatible PCI IDs from other vendors/brands. Change-Id: Ic115b1baa0be0dbaa81e4a17a2e466019d3f4a67 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* OxPCIe uart: Split PCI bridge controlKyösti Mälkki2014-04-092-132/+21
| | | | | | | | | | | | None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5237 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* uart: Redefine Kconfig optionsKyösti Mälkki2014-04-095-14/+20
| | | | | | | | | | | | | | | | | | | | | | | Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5311 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* console uart: Fill coreboot table entriesKyösti Mälkki2014-04-093-9/+46
| | | | | | | | | | | Also fixes the reported baudrate to take get_option() into account. Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5310 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* uart: Prepare to support multiple base addressesKyösti Mälkki2014-04-091-5/+8
| | | | | | | | | | | | Prepare low-level register access to take UART base address as a parameter. This is done to support a list of base addresses defined in the platform. Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5309 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* drivers/spi: Add support for adesto SPI flash partsChris Douglass2014-03-125-0/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for the following Adesto Technologies SPI Flash parts. AT25DF081 AT25DF321 AT25DF641 It has been tested on an Orion VPX7654 board populated with an AT25DF321A part. The "08" and "64" densities have not been tested. These parts are the successors of the Atmel AT26DF line that was spun out or purchased by Adesto. In this patch, adesto.c is identical to winbond.c with part entries for the Adesto parts. The datasheet for the AT25DF parts includes a "100MHz" programming command in addition to the "85MHz" command that is currently used but this patch does not add support for that enhanced programming mode. Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5225 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* intel/gma: Remove MCH register declarations.Vladimir Serbinenko2014-03-091-308/+0
| | | | | | | | | | | i915_reg.h re-declares some of MCH registers as seen through MCHBAR mirror. It's not currently used and we don't want any MCH registers in GFX. Change-Id: I5fa4711fee60d64316696b7ed713013de8759b54 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5318 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* console: Use single driver entry for UARTsKyösti Mälkki2014-03-041-8/+7
| | | | | | | | | | | UARTs now have unified prototypes and can use a single entry in the list of drivers for ramstage. Change-Id: I315daaf9a83cfa60f1a270146c729907a1d6d45b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5308 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* usbdebug: Move Kconfig under drivers/usbKyösti Mälkki2014-03-042-0/+95
| | | | | | | | | | | This menu may become a bit more complicated with addition of new USB hardware so move it out of console/. Change-Id: Ieb330675b9227a3e53d093f7c2b5a65e3842dc82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5307 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* SMM: Only have console with DEBUG_SMIKyösti Mälkki2014-03-041-3/+3
| | | | | | | | | | | Existing code compiled serial communication and printk() for SMM even when DEBUG_SMI was not selected. Change-Id: Ic5e25cd7453cb2243f7ac592b093fba752a299f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5142 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
* uart8250: Move under drivers/uartKyösti Mälkki2014-03-044-0/+384
| | | | | | | Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5236 Tested-by: build bot (Jenkins)
* uart8250mem: Unify calls with generic UARTKyösti Mälkki2014-03-043-19/+43
| | | | | | | | | | | NOTE: UART base for SMM continues to be broken, as it does not use the address resource allocator has assigned. Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5235 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* console: Fix includesKyösti Mälkki2014-03-044-3/+4
| | | | | | | | | | | | | | | Do not pull in console hw-specific prototypes everywhere with console.h as those are not needed for higher levels. Move prototypes for UARTs next to other consoles. Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5232 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* pl011 UART: Move under drivers/uartKyösti Mälkki2014-03-043-0/+64
| | | | | | | | | | Currently this is only a minimal stub to get console on qemu-armv7. Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5162 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* option: Add arch-agnostic get_option()Kyösti Mälkki2014-03-041-1/+1
| | | | | | | | | | We should not have pc80/ includes in console/. Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5157 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* uart8250: Fix and unify baudrate divisor calculationKyösti Mälkki2014-03-043-1/+63
| | | | | | | | | | | | | | | | | | | | | Divisor is a function of requested baudrate, platform-specific reference clock and amount of oversampling done on the UART reference. Calculate this parameter with divisor rounded to nearest integer. When building without option_table or when there is no entry for baud_rate, CONFIG_TTYS0_BAUD is used for default baudrate. For OxPCIe use of 4 MHz for reference was arbitrary giving correct divisor for 115200 but somewhat inaccurate for lower baudrates. Actual hardware is 62500000 with 16 times oversampling. FIXME: Field for baudrate in lb_tables is still incorrect. Change-Id: I68539738469af780fadd3392263dd9b3d5964d2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5229 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* nehalem: Replace video init.Vladimir Serbinenko2014-03-041-0/+5
| | | | | | | | | | | Old video init just replayed the sequence. This one actually computes the values. Change-Id: Ic1fe7a2e90dc2cc36ac0d8bcea5cfabc583f09a3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5270 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* drivers/intel/gma: Add EDID retrieving functions.Vladimir Serbinenko2014-03-045-2/+87
| | | | | | | | Change-Id: I64f2fcc5ad52d6a0188d02b28769001ada718c4f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5278 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* qemu: Support textmode gfx init.Vladimir Serbinenko2014-03-033-0/+22
| | | | | | | | | | Change-Id: I8b6b14b4fcf8df21d8bbf988d640b1efa013bd7f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5283 Tested-by: build bot (Jenkins) Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* drivers/spi: Sort SPI flash filesChris Douglass2014-02-281-2/+2
| | | | | | | | Change-Id: Id7e65065556ca7225969ca0afdb21eda24aeb967 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5260 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* usbdebug: Unify console APIKyösti Mälkki2014-02-202-5/+31
| | | | | | | | | | | | | Struct dbgp_pipe would not be suitable for use with xHCI. Just use an index, it is easy to setup in Kconfig if our future debug setup has separate pipes for console output and debugging/traceings. Change-Id: Icbbd28f03113b208016f80217ab801d598d443a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5227 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* console: Add drivers/uartKyösti Mälkki2014-02-173-0/+16
| | | | | | | | | | Also move UART related Kconfig options from top-level file. Change-Id: I4e407977cff6f6506f991600c98d6d264676d3f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5230 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* src/drivers/spi: introduce AMIC supportIdwer Vollering2014-02-175-1/+194
| | | | | | | | | | Add support for the AMIC A25L032 flash chip. Change-Id: Ie8d441a923c6fbd18c16440b4571321652d934d5 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/5252 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* usbdebug: Remove EHCI_DEBUG_OFFSETKyösti Mälkki2014-02-163-7/+30
| | | | | | | | | | Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* usbdebug: Split to USB host/deviceKyösti Mälkki2014-02-124-63/+90
| | | | | | | | | | | Top-level interface to console over USB mut not require low-level details of ECHI debug port internals. Change-Id: If3ca3b1f479e3f20976cd4abd8f5e682a58d5650 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5197 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* usbdebug: Split PCI EHCI partKyösti Mälkki2014-02-104-77/+139
| | | | | | | | | | | | There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* usbdebug: Fix data toggle on receiveKyösti Mälkki2014-02-101-2/+1
| | | | | | | | | | | | USB device end toggles data PID when we ACK'd the zero-length data packet. As USB host we need to toggle data PID too or the next data received would get discarded. Change-Id: I3203bc874c7ded9244c7548a666d7041a0fbb379 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4775 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
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