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* usbdebug: Improve receive speedKyösti Mälkki2014-02-101-0/+18
| | | | | | | | | | | Read from USB endpoint_in 8 bytes at a time, the maximum what EHCI debug port capability has to offer. Change-Id: I3d012d758a24b24f894e587b301f620933331407 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4700 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* QEMU debugcon: Move under drivers/emulation/qemuKyösti Mälkki2014-02-062-0/+44
| | | | | | | | | | | Also prepare this console for use in romstage. Change-Id: I26a4d4b5db1e44a261396a21bb0f0574d72aa86d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5136 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
* ne2k: Move under drivers/netKyösti Mälkki2014-02-064-0/+571
| | | | | | | | | Change-Id: I978b6009c09c31be4429f57be40ef82f438f7574 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5135 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* spkmodem: Move under drivers/pc80Kyösti Mälkki2014-02-062-1/+132
| | | | | | | | Change-Id: I46eb17ab19cea8759b3e4822019285cbe907e83a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5134 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
* usbdebug: Move under drivers/usbKyösti Mälkki2014-02-065-0/+1350
| | | | | | | | | | | Also relocate and split header files, there is some interest for EHCI debug support without PCI. Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* drivers/i2c/at24rf08c/lenovo_serials.c: Remove trailing whitespacePaul Menzel2014-02-021-1/+1
| | | | | | | | | | | The trailing whitespace breaks the Git commit hook `util/lint/lint-stable-003-wihitespace`. So remove it. Change-Id: I70e4ac71529884a9a4fabf2aa9a4ea6e0323b9d4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5092 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
* lenovo: Handle EEPROM/RFID chip.Vladimir Serbinenko2014-02-014-0/+214
| | | | | | | | | | | | | | | EEPROM/RFID chip present in thinkpad should be locked in a way to avoid any potential RFID access. Read serial number, UUID and P/N from EEPROM. This info is stored on AT24RF08 chip acessible through SMBUS. Change-Id: Ia3e766d90a094f63c8c854cd37e165221ccd8acd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4774 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
* spi: Add support for Winbod W25Q64DWAaron Durbin2014-01-281-0/+8
| | | | | | | | | | | | | | | | | | The W25Q64DW spi part is programatically equivalent to the other W25Q64 parts except it operates at 1.8V. Just add a new entry with the appropriate ID. BUG=chrome-os-partner:22292 BRANCH=None TEST=SPI controller can program the part. Change-Id: I65b0261223a9fefcb07477a43b6a3edb8228dd03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170011 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5077 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* pc80/keyboard: Ignore interface test failure.Vladimir Serbinenko2014-01-261-9/+18
| | | | | | | | | | On Asus A8N-E this test fails but if failure is ignored keyboard works. Change-Id: Ifeeff2f41537b35bc90a679f956fea830b94292c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4816 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* SPI: Add API for programmer-specific flashing.Vladimir Serbinenko2014-01-231-0/+15
| | | | | | | | Change-Id: I7a2f5b9ae74458b5ed6271b1c27842c61546dcd2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4712 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* keyboard.c: fix coding style with indentAndrew Wu2014-01-231-45/+55
| | | | | | | | | Change-Id: Ie8efa9fb9bdc65bf8015eec197f44c432e87d907 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3986 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* xpowers/axp209: Add helper to set voltages from devicetree configAlexandru Gagniuc2014-01-132-1/+76
| | | | | | | | Change-Id: I3ffe225b78f88c3c2d3a15292c43009e69413afb Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4638 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* xpowers/axp209: Allow voltages to be sepecified in devicetree.cbAlexandru Gagniuc2014-01-132-0/+34
| | | | | | | | | | | | This allows system voltages to be specified uniformly, rather than hardcoding them for each board. This will be used by cubieboard in an upcoming patch. Change-Id: I9dc2d3281d076c359c3fad13688649f7d36c0001 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4637 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* drivers: Add support for X-Powers AXP209 PMUAlexandru Gagniuc2014-01-138-0/+269
| | | | | | | | Change-Id: I1de0e656a38527b172af1d0b5bcd97acbfc03bf0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4591 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* drivers/spi/eon: Add EN25Q64Vladimir Serbinenko2014-01-121-0/+9
| | | | | | | | | | chip found in X230 if not using hardware sequencing. Change-Id: I6ded10d35bfdbbe3d54c4170dd7846c7833f5ff7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4616 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_contentVladimir Serbinenko2014-01-121-2/+2
| | | | | | | | Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4659 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
* Coding style: punctuation cleanup [1/2].Idwer Vollering2013-12-231-1/+1
| | | | | | | | | | Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4562 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* max77802: update headerDavid Hendricks2013-12-211-5/+10
| | | | | | | | | | | | | | | This adds #defines for BUCK2DVS1_1_2625V and BOOSTCTRL_OFF. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I363c73ff4a645da53973767fa4bfa2c120394af6 Reviewed-on: https://gerrit.chromium.org/gerrit/64303 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4426 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Refactor code containing aux callsFurquan Shaikh2013-12-212-2/+108
| | | | | | | | | | | | | Moved a lot of code from i915io.c to intel_dp.c with specific function calls Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc Reviewed-on: https://gerrit.chromium.org/gerrit/63950 Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4429 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flagsFurquan Shaikh2013-12-212-3/+11
| | | | | | | | | | | | | | Depending upon the values decoded from edid, the function decides the appropriate bits to be set in flags parameter (Important for fastboot to work correctly in kernel) Change-Id: I3b0f914dc2b0fd887eb6a1f706f87b87c86ff856 Reviewed-on: https://gerrit.chromium.org/gerrit/64265 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4423 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Add cpu transcoder attribute to intel dpFurquan Shaikh2013-12-214-0/+47
| | | | | | | | | | | | | | Also, used this attribute in the calculation of htotal and other registers Added intel_dp_* functions for m,n registers and dimension register calculations Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a Reviewed-on: https://gerrit.chromium.org/gerrit/64001 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4422 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Calculate transcoder flags based on pipe configFurquan Shaikh2013-12-213-0/+91
| | | | | | | | | | | | | Works fine with all three panels with the change of 6 bits per color. Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e Reviewed-on: https://gerrit.chromium.org/gerrit/63762 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4402 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* tpm: provide explicit tpm register accessAaron Durbin2013-12-211-100/+164
| | | | | | | | | | | | | | | | | | | | | An issue was observed using a specific vendor's TPM in that it chokes on access to registers that are not explicitly defined in the PC client specification. The previous driver used generic access functions for reading and writing registers. However, issues come to play when reading from the status register. It read it as a 32-bit value, but that read address 0x1b which is not defined in the spec. Instead of using generic access functions for the tpm registers provide explicit ones. To that end provide more high level wrapper functions to perform the semantic access required. Change-Id: I781b31723f819e1387d7aa25512c83780ea0877f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63243 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4388 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* rtd2132: implement full configurationAaron Durbin2013-12-212-21/+159
| | | | | | | | | | | | | | | | | It has been disseminated that the RTD2132 chip needs to be fully programmed for settings to take affect. Most of the settings are note documented very well and present themselves as magic values. Also, the wait time for starting the sequence needs to be bumped from 2ms to 60ms. Lastly, expose all the known settings through devicetree. Change-Id: I9eeea9c4a13ec20b8ce1c5297e43c4dd793d90e5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65857 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Remove PS/2 keyboard initialization on resume from S3Martin Roth2013-12-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | When we go through the resume path, there shouldn't ever be a need to initialize the PS/2 keyboard. The OS is going to reinitialize it anyway, and it just slows the resume. Verified Code flow in normal boot/S3 resume with print statements. Verified Keyboard was correctly disabled and flushed by booting to recovery mode screen while pressing keys on the integrated keyboard. Change-Id: I48bdca2fa2cc0c965401d10fef75cadb09d2e1e9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63648 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4396 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Pit: move parade writes to mainboard.cRonald G. Minnich2013-12-212-130/+14
| | | | | | | | | | | | | | | What gets written into the parade is highly mainboard-dependent. So the parade_writes array needs to be there. Change-Id: Ia382d9bf1929e67b7c14d7a09f5461b71866a16b Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61486 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* FUI: Fill in link_m and link_n valuesFurquan Shaikh2013-12-213-22/+54
| | | | | | | | | | | | | | | | | | | | | | | ... based on the EDID detailed timing values for pixel_clock and link_clock. Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n respectively. Other two undocumented registers 0x6f030 and 0x6f034 correspond to data_m and data_n respectively. Calculations are based on the intel_link_compute_m_n from linux kernel. Currently, the value for 0x6f030 does not come up right with our calculations. Hence, set to hard-coded value. Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e Reviewed-on: https://gerrit.chromium.org/gerrit/62915 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4381 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* SLIPPY: final changes for FUIRonald G. Minnich2013-12-213-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | The intel_ddi.c change I thought should be in but I don't see it. It just adds two functions back that we need. There are two new files for slippy annotated with comments about how it needs to evolve. That said, this code has been tested on 3 different panels. Both dev and non-dev usages work. physbase initialization to static value removed. Moved spin calls to intel_dp_* Change-Id: I0480af45c21c7dedcaff7e8be729f0eb554ec78a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61136 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4370 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
* rtd2132: Add driver for Realtek RTD2132 LVDS bridgeDuncan Laurie2013-12-216-0/+184
| | | | | | | | | | | | This driver allows the mainboard to enable spread spectrum clocking at 0.5%, 1.0%, and 1.5% with devicetree settings. Change-Id: I59c61e67aa8e951fd9904ad951deb6d0ba29669e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61894 Reviewed-on: http://review.coreboot.org/4365 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
* qemu/videoinit: Set required fields in fake EDIDVladimir Serbinenko2013-12-162-0/+6
| | | | | | | | | | | | | | x_resolution, y_resolution and bytes_per_line were not inited. Without them coreboot sweared that screen is 1108630x1142817 and payload tried to draw on such a big screen. Change-Id: I0d0277a20c7e1976c27af4a57651ab2be0f9c5d7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4535 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* drivers/pc80: Add ACPI description.Vladimir Serbinenko2013-12-141-0/+51
| | | | | | | | | | | | | AT controller needs an ACPI node, otherwise FreeBSD doesn't detect keyboard and mouse. Currently each SuperIO adds its own description. This one should be used in the future instead. Change-Id: Iaad5ed3846c6d9f467a02a286a1e6f60a3607af5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4518 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Add kernel-derived support functions for DDI.Ronald G. Minnich2013-12-073-0/+114
| | | | | | | | | | | | | | | | | | | Newer mainboards that use haswell -- and, presumably, chipsets to come -- need some support functions. Add them in the drivers/intel/gma directory. Currently, this is one file: intel_ddi.c, but more may come. Compilation of this file is controlled by INTEL_DDI, defined in the Kconfig as default n and used in the Makefile.inc Change-Id: I501ee291c0d4589925ed3e478f67106337fcad31 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60612 Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4337 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* elog: handle ROM_SIZE differences from detected flash sizeAaron Durbin2013-12-071-2/+26
| | | | | | | | | | | | | | | | | | The elog code calculates flash offsets and their equivalent addresses in the memory address space. However, it assumes the detected flash size is entirely mapped into the address space. This can lead to incorrect calculations. Add code to allow ROM_SIZE to be less than detected flash size. The underlying assumption is that the first ROM_SIZE bytes are programmed into the larger device. Change-Id: Id848f136515289b40594b7d3762e26e3e55da62f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60501 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4332 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Add in the Makefile bits for the new intel gma driverRonald G. Minnich2013-12-062-0/+2
| | | | | | | | | | | | | | The Intel GMA driver is in, this CL splices in the Makefile bits. Change-Id: Icf42a537575b8cc90a679ec1fc15b09294630611 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60346 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4331 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* FUI: add intel_dp driver derived from kernel functionsRonald G. Minnich2013-12-058-0/+2311
| | | | | | | | | | | | | | | | | | These functions are not all used yet, but do compile and are partially used in the FUI testing. They were extracted from the 3.4 kernel using coccinnelle filters. The .c files are only compiled in if CONFIG_INTEL_DP is set. Change-Id: Id95622a75aa02b496c9ea4717cb143394a8332e3 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60245 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4329 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* haswell: pull in the init code for FUIRonald G. Minnich2013-12-051-0/+4684
| | | | | | | | | | | | | | | | | | | | | | | | Removed two unnecessary register sets, and did the power well a bit more correctly. Also, added a register definition include file so we can used constants instead of magic numbers. We also set registers to common initialized values that are needed for FUI, VBIOS, and kernel. This set of registers appears to be an absolute bare minimum. Since we're hoping to use FUI for all chipsets from this one forward, we unconditionally do the setting here. Signed-off-by: Ronald G. Minnich <rminnich@google.com> Change-Id: Ife3f661ba010214d92b646b336f2b06645119f17 Reviewed-on: https://gerrit.chromium.org/gerrit/59988 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4328 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* elog: Get rid of the descriptor type and some unnecessary wrappersGabe Black2013-12-022-169/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was always exactly one elog descriptor declared and initialized, but its contents were being accessed through a pointer that was passed back and forth between functions instead of being accessed directly. This made the code more verbose than it needed to be and harder to follow. To address this the descriptor type was eliminated, its contents were turned into individual global variables, and various functions were adjusted to no longer take the descriptor as an argument. Similarly, the code was more verbose and complicated than it needed to be because of several wrapper functions which wrapped a single line of code which called an underlying function with particular arguments and were only used once. This makes it harder to tell what the code is doing because the call to the real function you may already be familiar with is obscured behind a new function you've never seen before. It also adds one more text to the file as a whole while providing at best a marginal benefit. Those functions were removed and their callers now call their contents directly. Built and booted on Link. Ran mosys eventlog list. Cleared the event log and ran mosys eventlog list again. Added 2000 events and ran mosys eventlog list. Cleared the log again and ran mosys eventlog list. Change-Id: I4f5f6b9f4f508548077b7f5a92f4322db99e01ca Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49310 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4245 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* elog: Stream line the elog driver.Gabe Black2013-12-022-193/+79
| | | | | | | | | | | | | | | | | | | | | | The elog driver's design was a bit more elaborate than it really needed to be since it no longer had to keep track of multiple copies of the log in flash and also in memory. This change streamlines it by removing unnecessary compartmentalization of some bits of code, and some variables which tracked the last entry added which were never used. Built and booted on Link. Ran mosys eventlog list. Added 2000 events to the event log and ran mosys eventlog list again. Cleared the log by echoing 1 into /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list. Change-Id: I7d4cdebf2f5b1f6bb1fc70e65eca18f71b124b18 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49309 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4244 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* elog: Merge elog_validate_and_fill into elog_init_descriptor.Gabe Black2013-12-021-23/+16
| | | | | | | | | | | | | | | | | | | | | | | | elog_validate_and_fill was called in exactly one place, in elog_init_descriptor. It didn't actually do what its name implied since the data in the event log was already "filled" by elog_init_descriptor. Likewise elog_init_descriptor was delegating an important part of its own job, scanning through the list of events, to elog_validate_and_fill. Since one function was basically just a displaced part of the other which couldn't really stand on its own, this change merges them together. Built and booted on Link. Ran mosys eventlog list. Added 2000 events with the SMI handler and ran mosys eventlog list again. Change-Id: Ic899eeb18146d0f127d0dded207d37d63cbc716f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49308 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4243 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* elog: Get rid of elog_reinit_descriptor.Gabe Black2013-12-021-26/+19
| | | | | | | | | | | | | | | | | | | | | This function was just a wrapper around elog_init_descriptor, and all it did was pass the current backing store location and size back in so it would be reused. Those values, which never change, are now set in elog_setup_descriptors, eliminating those parameters to init and eliminating the need for _reinit_. Built and booted on Link. Ran mosys eventlog list. Added 2000 events to the log and ran mosys eventlog list again. Change-Id: I133768aa798dfc10f32e14db95235a88666890c3 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49307 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4242 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* elog: Eliminate the second in memory copy of the event log.Gabe Black2013-12-022-162/+55
| | | | | | | | | | | | | | | | | | | | | | The event log driver keeps two copies of the event log in memory, one to take the place of the historically memory mapped image of flash which is now read and written manually, and one originally intended to be an in memory cache of flash. Since both are now just copies in memory, there's no value in having them both and keeping them in sync. Built and booted on Link. Ran mosys eventlog list. Added 2000 events to the log and ran mosys eventlog list again. Cleared the log by echoing a 1 into /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list again. Change-Id: Ibed62a10c78884849726aa15ec795ab2914afc35 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49306 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4241 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Make elog_shrink not depend on having seperate memory/flash descriptors.Gabe Black2013-12-021-13/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | The way elog_shrink currently works is that it completely clears the data in the flash/flash descriptor and then recreates it using the part of the log it's going to keep as stored in the memory descriptor. That scheme depends on there being to independent copies of the log. This change reworks elog_shrink so that it moves the data it wants to keep within a single descriptor and then propogates it to the other and to flash intact. This way, when one of the descriptors goes away, all we have to do is remove the code that would update it. Built and booted into ChromeOS on Link. Ran mosys eventlog list. Added 2000 events to the log and ran mosys eventlog list again. Echoed a 1 into /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list. BRANCH=None Change-Id: I50d77a4f00ea3c6b3e0ec8996dab1a3b31580205 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49305 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4240 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* elog: Get rid of the staging_header variable.Gabe Black2013-12-022-21/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The header is at the start of the log. There's no reason to either keep a seperate pointer to it, or to keep a copy of it in some other bit of memory. Built and booted on Link and used 'mosys eventlog list' to list the contents of the log. Ran for x in $(seq 1 2000); do cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog; done And ran mosys eventlog list again to verify that the log had been shrunk correctly. Change-Id: I2afcd52c0ce5bbb662ac56f2895cdbea28d5c2ce Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49304 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4239 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* qemu: minor bochs cleanupsGerd Hoffmann2013-11-261-2/+4
| | | | | | | | | | | | Add a comment, tweak spacing a bit, addr variable doesn't need to be global any more. Change-Id: Id8d8a7babce671243351074f7ac52a5c8c264de5 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/4274 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* pc80/mc146818rtc: Return an error code rather than an integerAlexandru Gagniuc2013-11-251-23/+25
| | | | | | | | | | | Do not return hardcoded numerical values to communicate succes/failure, but instead use an enumeration. Change-Id: I742b08796adf136dce5984b702533f91640846dd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4265 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* RTC: Skip rtc_init() in S3 resume pathStefan Reinauer2013-11-251-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | In addition to not clearing the pending interrupts, we also don't want to reset the RTC control register when booting with an S3 resume. On most new systems, when the RTC well is losing power, we will also lose state that is required to perform a resume, so we end up in a normal boot anyways. Hence don't do any RTC initialization in the S3 resume path. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I73b486082faa741e9dccd15f2b8e3a8399c98f80 Reviewed-on: https://gerrit.chromium.org/gerrit/56826 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Derek Basehore <dbasehore@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4206 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* elog: Check for successful flash erase in elog_shrinkDuncan Laurie2013-11-251-1/+8
| | | | | | | | | | | | | | | A parrot device with a bad flash part has been seen to hang in the elog_shrink code becuase the flash was not successfully erased and it gets stuck in a loop trying to shrink the log and then add an event. Change-Id: I8bb13dbadd293f9d892f322e213c9255c8e9acb3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56405 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4186 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* elog: Make sure the elog data structures are initialized in elog_clear.Gabe Black2013-11-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | If elog_clear is called before other elog functions, for instance if it's called through an SMI immediately after the system boots, then the elog data structures won't have been set up and the system will go off the deep end. This change adds a call to elog_init to elog_clear to make sure things things are always initialized before we start using them. Before this change, this command would cause the system to lock up if run immediately after boot: echo 1 > /sys/firmware/gsmi/clear_eventlog After this change, that results in the log being cleared correctly. Change-Id: I45027f0dbfa40ca8c581954a93b14b4fedce91ed Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49303 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4144 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* qemu: cirrus native video initVladimir Serbinenko2013-11-252-0/+351
| | | | | | | | | | | | Recent commit proposal by Ron Minnich proposes to move to native gfx init for qemu. Unfortunately we didn't have native init for default qemu video (cirrus) Here is one extracted from GRUB one which I wrote couple of years ago. Change-Id: Icb89cf918ef5d276bcc703c48c568e7b9c1be756 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4270 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* bochs: add support for native graphicsRonald G. Minnich2013-11-251-29/+13
| | | | | | | | | | | | | | | | | | | | | Per our discussions with Gerd, qemu will now always do native graphics on coreboot. The VGA BIOS capability is not needed and will no longer be supported. Attempts to build without native graphics will result in an error. This code builds for both x86 emulation targets. I'm hitting an issue testing that is unrelated to coreboot; if someone can test, that would be helpful. Be sure to start qemu with -vga std. We also add a test for the PCI BAR being zero and return silently if it is. Change-Id: I66188f61e1bac7ad93c989cc10f3e0b55140e148 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/4258 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
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