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* Skylake: Add ASL code to enable GPIO controllerArchana Patni2015-08-144-103/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables GPIO controller for skylake. It adds community base addresses and offset for Community0, Community1, and Community3. Community2 is not exposed in BIOS or enabled in the kernel driver. Also, clean up the carry over GWAK implementation from BDW. BRANCH=None BUG=chrome-os-partner:42393 TEST=cat /sys/kernel/debug/gpio should list of GPIOs TEST=export a GPIO pin using /sys/class/gpio/export Original-Change-Id: I891c40589d3dbd796cf593626472c7b5674a1ae0 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291230 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Change-Id: I7481ce682ccae872fddf81b3188c3415d5d3f7d9 Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Reviewed-on: http://review.coreboot.org/11191 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.cAaron Durbin2015-08-141-8/+7
| | | | | | | | | | | | | | | | | | | | | | | acpi_is_wakeup_s3() was introduced in upstream coreboot while the FSP support code was written. Move to using that instead of using the romstage_handoff structure directly. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I71601a4be3c981672e25e189c98abb6a676462bf Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290720 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2ae4d9906e0891080481fb58b941921922a989d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11190 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* libpayload: Do not gate USB_DWC2 on USB_HIDDavid Hendricks2015-08-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | This forward-ports the change from CL:277155 since the Kconfig file was renamed from Config.in. BUG=chrome-os-partner:41416 BRANCH=none TEST=built and booted on Mickey, keyboard works at dev screen Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ibffa5188df51ecd7b8bdd631d4b767ec64130819 Original-Reviewed-on: https://chromium-review.googlesource.com/291138 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Change-Id: Iebb1da6ec8c7886a6eb9ebcc67b59d617496c555 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/11188 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@google.com>
* libpayload: usb: xhci: Count new Max Scratchpad Bufs bits from XHCI 1.1Julius Werner2015-08-142-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The 1.1 revision of the XHCI specification added an extra 5 bits to the Max Scratchpad Bufs field of HCSPARAMS2 that newer controllers make use of. Not honoring these bits means we're not allocating as many scratchpad buffers as the controller expects, which means it will interpret some uninitialized values from the end of the pointer array as scratchpad buffer pointers, which obviously doesn't end well. Let's fix that. BRANCH=none BUG=chrome-os-partner:42279 TEST=Makes a USB-related memory corruption issue disappear. Original-Change-Id: I7c907492339262bda31cdd2b5c0b588de7df8544 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291681 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iba1007bfebffe1f564f78bb875fff9ba0fe11a38 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11189 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* libpayload: usb: dwc2: fix short packet transferYunzhi Li2015-08-141-11/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | If short packet detected, stop this transfer and return the actual transferred size BUG=chrome-os-partner:42817 TEST=Netboot could run well BRANCH=None Original-Change-Id: Icb4317f48aa04ac15bb1886b81d2e3c472d123d0 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/288215 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-(cherry picked from commit d372343b4e3d664ce2d76dbf55a5061b5d496bba) Original-Reviewed-on: https://chromium-review.googlesource.com/291064 Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Change-Id: I43d9edffe2074c037f2df203621863e54d2597fa Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Reviewed-on: http://review.coreboot.org/11187 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: clear write-1-to-clear fields in power regsAaron Durbin2015-08-141-13/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Explicitly clear all write-1-to-clear fields in the appropriate power state registers. That way stale state isn't left around from boot to boot. The MMIO PMC registers are always added such that the resource can be accessed from reg_script. It doesn't hurt to add the resource, and it's actually more informative by attaching the actual resources owned by the device. BUG=chrome-os-partner:43625 BRANCH=None TEST=Built and boot glados. Did global reset. Noticed bits set. Did normal reset and saw those same bits no longer set. Original-Change-Id: Idd412bd6bf2c6c57b46c74f9411bdf8413ddd83e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290339 Change-Id: Ibef1aefedf6ba006f17f9f94998a10b39cc6bfec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11186 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: fix invalid GNVS base addressAaron Durbin2015-08-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Leaving a sentinel 0xC0DEBABE and fixing it up is is the old way of setting the correct base address for GNVS. One just needs to reference NVSA which is already filled in by the skylake ACPI code. BUG=chrome-os-partner:43611 BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. /sys/firmware/log shows up as well as ramoops using the correct address. Original-Change-Id: I1d4979b1bb65faa76316a4ec4c551a7b9b9eed32 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290338 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I25efea73a383215f9365ce91230f79516b0201a6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11185 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: enumerate the SMI status fieldsAaron Durbin2015-08-142-34/+35
| | | | | | | | | | | | | | | | | | | | | Provide #defines for the bit fields in the SMI status register. This allows for one to set the callback accordingly without hard coding the index. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I3e61d431717c725748409ef5b543ad2eb82955c4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289802 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I1a91f2c8b903de4297aaa66f5c6ff15f1b9c54f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11184 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: set DISB in GEN_PMCON_A register properlyAaron Durbin2015-08-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM training is complete. However, as a 8-bit write was being performed the bit was never being set. BUG=chrome-os-partner:43516 BRANCH=None TEST=Built and booted to kernel. Rebooted. Noted full memory training was not being peformed. Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290337 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11183 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: fill out gen_pmcon_* bitfieldsAaron Durbin2015-08-142-4/+38
| | | | | | | | | | | | | | | | | | | | | | Open coding bitfields is really annoying as no one knows what they are unless you have a doc in front of you. Fill in the bitfields for the GEN_PMCON_A and GEN_PMCON_B registers. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Id48de68eaa3896c17d5da2ffb0bcf17062f73e5e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290336 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I968be9736419e26a771e0a0c3c964d540fbb1efe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11182 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* glados: enable SMBus deviceAaron Durbin2015-08-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | In order to run with the debug FSP the SMBus device needs to be enabled. Additionally, the TCO block lives within the SMBus device so if TCO is to be employed then the SMBus device needs to be enabled as a prerequisite. BUG=chrome-os-partner:42407 BRANCH=None TEST=Buit and booted into kernel. Original-Change-Id: I269650fa5222b4741ef495188dff1f4b8176fe89 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290364 Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia1f72ea7bd70728de83cdff07df9810a326266c2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11181 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: do not overlap resourcesAaron Durbin2015-08-141-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | FSP was setting up the TCO registers to be mapped at 0x400. However, the SMBus initialization in romstage was mapping its I/O BAR to 0x400 as well. The result seemed to cause the TCO register to be hidden. However, the board was rebooting in depthcharge when the SMBus device was enabled from a TCO timeout. As the TCO timer was halted before the double resource assignment it's not clear how the TCO was getting re-enabled. In either case, the current behavior is wrong. BUG=chrome-os-partner:42407 BRANCH=None TEST=Built and booted glados w/ SMBus enabled. Original-Change-Id: I43c0d67a76abac51ccfd5105245792981fbcd04c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290363 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I3839290768c27626c3fd2d67d5de94c291c1386e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11180 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* libpayload: usb: Fixup wrong use of configChunfeng Yun2015-08-141-2/+2
| | | | | | | | | | | | | | | | | | | | | replace CONFIG_LP_XHCI_MTK_QUIRK by CONFIG_LP_USB_XHCI_MTK_QUIRK BRANCH=none BUG=none TEST=Rev0-oak Original-Change-Id: I68f58ed3b02caa7cef8f0f60a4a8f5e9755c97a7 Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290522 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I316712e99e0b44d292dab27cf66e26837dc2e957 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-on: http://review.coreboot.org/11179 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* libpayload: xhci: Carry over fixes from Chromium treeJulius Werner2015-08-142-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch re-adds a few fixes that originally went into the chromeos-2013.04 tree. I kinda seem to have slipped them into the backport of Nico's original XHCI patch (crosreview.com/168097) instead of making a new change, which was not very clever and caused them to be forgotten in the later upstreaming wave. Changing internal XHCI error numbers is just a cosmetic change to make them uniquely identifyable in debug output. Bumping the timeout to 3 seconds is an actually important fix since we have seen mass storage devices needing that much in the past. BRANCH=None BUG=None TEST=Diffed payloads/libpayload/drivers/usb between chromeos-2013.04 and chromeos-2015.07, confirmed that no serious differences remain. Original-Change-Id: I03d865dbe536072d23374a49a0136e9f28568f8e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290423 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I5d773d3a23683fb2164916cc046f4a711b8d259e Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11178 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* cbfs: fix printf for 64bit architecturesDaisuke Nojiri2015-08-141-3/+3
| | | | | | | | | | | | | | | | | | | | BUG=none BRANCH=smaug TEST=Built for Smaug Original-Change-Id: I7ff577f97252265ca6c96963ca44a6fbd0de9f7a Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290049 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-(cherry picked from commit 9cff308653766ea81978214e99a3d740aff4dbbe) Original-Reviewed-on: https://chromium-review.googlesource.com/290116 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: I5dcc17e0a42b46350fe6c398767f8155bdd0fd9d Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/11177 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: use native gpio configuration for uartAaron Durbin2015-08-141-57/+6
| | | | | | | | | | | | | | | | | | | | Instead of open coding the UART2 gpio configuration use the support library. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I9637cb995d51b67eb320650d92f8518de0280dca Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289801 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I7f0e6599df983323f773f1ec6600537c20c15b11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11176 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* glados: move to native gpio configurationAaron Durbin2015-08-144-321/+178
| | | | | | | | | | | | | | | | | | | | | | Instead of relying on FSP to do gpio configuration in one place use the native support in coreboot. This also removes the open coded configuration of the memory configuration ids. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I4655221d821d91a2270d774305a02d6bd5c3959c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289800 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2e66242d050c3825f6bc65d3d2c7f51d2cdfbd73 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11175 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: provide native gpio functionalityAaron Durbin2015-08-145-629/+1285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It's important to be able to configure the gpio pads at various stages instead of a single place using FSP. Without this support there is a lot of duplicated open-coded pad configuration taking place both within the SoC code and mainboards. Current limitation is that all GPIOs are in ACPI mode. i.e. The HostSW ownership register sets the pad configuration to only update GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. The GPI_STS update is masked within the GPIO community registers. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Id8a00e99c7a4c3912de2feaff9cea12b402f2c68 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289789 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I4c86b47ac5ab004f2bfd7cb07dd23c458f7dbb7c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11174 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabledTimothy Pearson2015-08-141-9/+25
| | | | | | | | | | | | | | | | In the wake of the recent Intel "Memoy Sinkhole" exploit a code review of the AMD SMM code was undertaken. While native Family 10h support does not appear to be affected by the same SMM flaw, it also does not require SMM to function. Therefore, the SMM memory range initialization should only be executed if SMM will be used on the target platform. Change-Id: I6531908a7724933e4ba5a2bbefeb89356197e8fd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11211 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* libpayload: usb: don't prematurely free the usb deviceAaron Durbin2015-08-131-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before the controller's destroy_device() could interrogate the usbdev_t object usb_detach_device() was freeing and NULLing out the pointer. That results in all callers who needed that object to start accessing random bits of memory. This eventually led into free()ing memory it shouldn't which corrupted the allocator's state. Eventually, all forward progress was lost by way of a single ended linked list turning into a circular list. The culprit seems to be a bad merge in commit e00ba21. BUG=chrome-os-partner:43419 BRANCH=None TEST=Can boot into OS now w/o "hanging" on glados. Original-Change-Id: I86dcaa1dbaf112ac6782e90dad40f0932f273a1f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290048 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Change-Id: I9135eb0f798bf7dbeccc7a033c3f8471720a0de5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11173 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: fix serial port with new code baseAaron Durbin2015-08-137-12/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | Many Kconfig options changed in coreboot.org since skylake was first started. Fix Kconfig option name changes, and also provide a common option, UART_DEBUG that can be selected to select all the necessary options. Note: It's still a requirement to manually unset the 8250IO option because that's unconditionally set. BUG=chrome-os-partner:43419 BUG=chrome-os-partner:43463 BRANCH=None TEST=Built glados. Booted into kernel. Kernel reboots somewhere. Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289951 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11172 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* glados: Enable wake from EC via LAN_WAKE#Duncan Laurie2015-08-132-0/+4
| | | | | | | | | | | | | | | | | | | | Enable the Deep Sx pins to allow wake from the EC via LAN_WAKE#. Report the EC wake pin LAN_WAKE as GPE[112]. BUG=chrome-os-partner:43079 BRANCH=none TEST=suspend/resume on glados with wake from keyboard Original-Change-Id: I99664e1e406d15e7460046a6168cbd3a377aaca4 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288921 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I19db144ed5db183f47af03340886a5e770af8bc8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11171 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: Add Deep Sx configuration for wake pinsDuncan Laurie2015-08-133-0/+26
| | | | | | | | | | | | | | | | | | | | Add support for enabling various pins in Deep Sx by setting a register in the mainboard devicetree. BUG=chrome-os-partner:43079 BRANCH=none TEST=build and boot on glados Original-Change-Id: I1b4fb51f72b88bdc49096268bdd781750dcd089d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288920 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7555a92fecc6e78b579ec0bc18da202cb0c824e2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11170 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* uart8250mem: provide uart_fill_lb()Aaron Durbin2015-08-131-0/+19
| | | | | | | | | | | | | | | | | | | | | There was no implementation for uart_fill_lb() in the 8250mem driver. Rectify this so when 8250MEM and CONSOLE_SERIAL are employed then the build doesn't fail. BUG=chrome-os-partner:43419 BRANCH=None TEST=Built with glados using 8250MEM Original-Change-Id: I35d6b15e47989c1854ddcee9c6d46711edffaf3e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289899 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: I972b069a4def666f509268816de91ed6c0f655d9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11169 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: remove CBFS_SIZE option in SoC directoryAaron Durbin2015-08-132-11/+1
| | | | | | | | | | | | | | | | | | | | | | CBFS_SIZE is living as a mainboard attribute. Because of the Kconfig include ordering the SoC *cannot* set the default. Remove from the soc Kconfig and add a default Kconfig for SOC_INTEL_SKYLAKE. BUG=chrome-os-partner:43419 BRANCH=None TEST=built glados Original-Change-Id: I8808177b573ce8e2158c9e598dbfea9ff84b97c7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289833 Original-Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: Icf52d7861eee016a35be899e5486deb0924a0f3c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11168 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* skylake: fix garbled patch from upstreamAaron Durbin2015-08-131-13/+12
| | | | | | | | | | | | | | | | | | | | | | In the review process for http://review.coreboot.org/#/c/11052/ the code was mangled and the result was unbuildable code. Fix this. BUG=chrome-os-partner:43419 BRANCH=None TEST=Can actually build bootblock. Original-Change-Id: I5bc63b8c435dbf025f1c334e9a1bc4a9da2b4902 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289788 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: Id0f67d8b74fa9146bf01990f599d538222f7e0e2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11167 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* x86: parameterize asl_template for CBFS inclusionAaron Durbin2015-08-132-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The asl_template previously unconditionally included dsdt.aml. However, COMPILE_IN_DSDT=y results in the dsdt.aml being linked directly into ramstage. Thus the information is duplicated. The inclusion of this file unconditionally throws some errors as certain assets need to be included in CBFS. However, as there isn't fine-grained ordering control in how files are added fixed resource requirements for other assets collide result in failure to build. To remedy both things, provide a 2nd argument to asl_template which defaults to 'y' for CBFS addition. In the COMPILE_IN_DSDT=y case pass 'n' so that dsdt.aml is no longer added. BUG=chrome-os-partner:43419 BRANCH=None TEST=For glados: Built with COMPILE_IN_DSDT=y. dsdt.aml not included. Built with COMPILE_IN_DSDT=n. dsdt.aml was included. Original-Change-Id: I4767e5be2915c1732251fe415017f30314c5efc9 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289840 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id1828627ba0a034eb05b2fe23be76e19f3040444 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11166 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
* cbfstool: unify actual file creationPatrick Georgi2015-08-131-32/+5
| | | | | | | | | | | | | | | After the preparation in earlier commits, it is now possible to handle the more general case of position independent files using the special code path for fixed location files. This leads to a single place where non-empty cbfs file headers are actually written into the image, allowing us to move it up the chain more easily. Change-Id: I8c1fca5e4e81c20971b2960c87690e982aa3e274 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11222 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/common/intel: Reset is not dependend upon FSPLee Leahy2015-08-131-1/+0
| | | | | | | | | | | | | | | | | | | | | Remove dependency of common reset code on FSP BRANCH=none BUG=None TEST=Build and run on Braswell and Skylake Original-Change-Id: I00052f29326f691b6d56d2349f99815cafff5848 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286932 Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7f59f0aad7dfae92df28cf20fff2d5a684795d22 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: http://review.coreboot.org/11165 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
* cbfstool: move tests for fixed-location files earlierPatrick Georgi2015-08-131-21/+20
| | | | | | | | | | | | ... and the assert is gone. The actual action of adding a just-right file can be moved after the tests since it's exactly the condition those tests don't continue or break on. Change-Id: I6d0e829e0158198301136ada9a0de2f168ceee3f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11221 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* amd: raminit sysinfo offset fixAaron Durbin2015-08-138-25/+30
| | | | | | | | | | | | | | | | | | | The sysinfo object within the k8 ram init is used to communicate progess/status from all the nodes in the system. However, the code was assuming where the sysinfo object lived in cache-as-ram. The layout of cache-as-ram is dynamic so one needs to do the lookup of the correct address at runtime. The way the amd code is compiled by #include'ing .c files makes the solution a little more complex in that some cache-as-ram support code needed to be refactored. Change-Id: I6500fa7b005dc082c4c0b3382ee2c3a138d9ac31 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10961 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* cbfstool: prepare moving tests earlierPatrick Georgi2015-08-131-12/+14
| | | | | | | | | | | The assert() makes sure the if() holds true. But that assert won't survive for long. Change-Id: Iab7d2bc7bfebb3f3b3ce70dc5bd041902e14bd7a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11220 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbfstool: factor out creating a cbfs file headerPatrick Georgi2015-08-132-2/+20
| | | | | | | | | | | We will want to create headers that live outside the final image at some point (eg. to build the file before we even know where to place it). Change-Id: Ie4c0323df8d5be955aec3621b75309e8f11fae49 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11219 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbfstool: Make cbfs_create_empty_entry build a more complete headerPatrick Georgi2015-08-132-13/+14
| | | | | | | | | | | Pass the file type into it instead of creating an entry, then modifying the header field again after the fact. Change-Id: I655583218f5085035b0f80efff7f91a66b5b296e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11218 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbfstool: honor larger-than-usual header sizes in cbfs_add_entry_at()Patrick Georgi2015-08-131-4/+5
| | | | | | | | | | | | If an earlier stage built a larger header, cbfs_add_entry_at() shouldn't decide to go with the most boring, least featureful header type (and its size) instead. Change-Id: Icc5dcd9a797a0f3c42f91cddd21b3b3916095b63 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11217 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbfstool: allow file data converters to modify the header sizePatrick Georgi2015-08-131-5/+7
| | | | | | | | | | | The idea is that they can at some point add extended attributes to the header. That also needs to be passed, but let's start simple. Change-Id: I80359843078b149ac433ee3d739ea192592e16e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11216 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbfstool: calculate header size in cbfs_add_component()Patrick Georgi2015-08-131-1/+4
| | | | | | | | | | | It will at some point create the header, and pass it with its size. We can start with the size already. Change-Id: I8f26b2335ffab99a664d1ff7bc88e33ed62cf9ca Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11215 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbfstool: expose cbfs_calculate_file_header_size()Patrick Georgi2015-08-132-1/+3
| | | | | | | | | | | Headers vary in size soon, and more places need to be able to calculate their size. Change-Id: I30761bb9da0756418993dee21d8fa18cf3174c40 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11214 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbfstool: allow passing a precalculated header size into cbfs_add_entry()Patrick Georgi2015-08-133-7/+10
| | | | | | | | | | | | This is in preparation of creating the cbfs_file header much earlier in the process. For now, size is enough because lots of things need to move before it makes sense to deal with cbfs_file at a higher level. Change-Id: I47589247c3011cb828170eaa10ef4a1e0f85ab84 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11213 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbfstool: test for duplicate files earlierPatrick Georgi2015-08-131-6/+5
| | | | | | | | | | No need to read the file before bailing out. Change-Id: Ida7226c6ec227e1105724cdb1e5a0927217a69c7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11212 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbfstool: add cbfs file attribute structurePatrick Georgi2015-08-131-0/+10
| | | | | | | | | | | This is a generic structure, not unlike the cbtables design, based on which we can build specialized TLV data structures. Change-Id: I98a75eef19f049ad67d46cdc2790949dcd155797 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10937 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* buildgcc: Fix the options checkzbao2015-08-131-2/+2
| | | | | | | | | | | | | | | | | 1. Add -P|--package to build iasl 2. Remove -G|--skip-gdb, which was to skip gdb. 3. Add -S|--scripting to build gdb 4. Remove -C|--clang, which was to build clang. All these changes are aligned with the options parsing below. The help text is correct. Change-Id: I897ea5e8ab002086e45bf05ff33230815b246057 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11158 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* board-status: move board status back to $TMPDIRPatrick Georgi2015-08-131-3/+7
| | | | | | | | Change-Id: I05a8c246384abfc954cfcf163a68cca71aa6b2f0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11224 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
* getac/p470: enable early cbmem initPatrick Georgi2015-08-131-0/+1
| | | | | | | | | Change-Id: I4afec92c57c6af4c99858afae53fa7746f47bc7a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11159 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* getac/p470: Enable native VGA initPatrick Georgi2015-08-132-0/+7
| | | | | | | | Change-Id: I6c5a2324d1a9e21f4e052678be8f0e0dbfed6494 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11136 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* getac/p470: Add C-State valuesPatrick Georgi2015-08-131-1/+21
| | | | | | | | | | | | Derived from what the vendor BIOS is doing. Change-Id: Ie2cba7b86b6bb3f1dcc4a5e1c189aa45d0aab109 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: fwts 15.08 Reviewed-on: http://review.coreboot.org/11142 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* getac/p470: Clean up SIO access in ACPIPatrick Georgi2015-08-111-65/+45
| | | | | | | | | | This adapts Ia5101d5a1 for the p470. Change-Id: Ib09a0bc58fddd6240834cc890f00df91a74f4161 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11160 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* chromeos: Allow for VB_SOURCE overridePaul Kocialkowski2015-08-111-1/+1
| | | | | | | | | | | | One may prefer to include vboot from another directory than 3rdparty for convenience. This is especially the case in Libreboot, where 3rdparty is not checked out at all. Change-Id: I13167eb604a777a2ba87c3567f134ef3ff9610e4 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11116 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* board_status: use command -v over which(1)Patrick Georgi2015-08-101-2/+2
| | | | | | | | | | | The script is pretty linux specific as-is, but more portability won't hurt. Change-Id: I33e18606bea4e23043d748e3fe66a345e720d389 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11151 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* what-jenkins-does: Add building chromeos configurationsPatrick Georgi2015-08-101-0/+2
| | | | | | | | | | | | This prevents us from inadvertedly breaking Chrome OS' configurations. They're built in addition to the normal configurations for each boards, to accomodate all use cases on these devices. Change-Id: I772a47dca8815f47c12f6fd4405ae28c7c997aa8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11104 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
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