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* util/board_status/board_status.sh: set its executable flagPaul Menzel2014-04-291-0/+0
| | | | | | | | | Change-Id: I58f6d356bf1625ee205a536ee95c08294891b123 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5171 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* AGESA SPI: Fix Kconfig optionsKyösti Mälkki2014-04-293-3/+7
| | | | | | | | | | | | | Option AMD_SB_SPI_LEN leaked to non-AMD configs. Option SPI_FLASH is compulsory with HAVE_ACPI_RESUME. Change-Id: Ib84c4d9e4fdf670b32b0cae7280fcbb6d3aecaf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5606 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* SPI: Use common dependency in KconfigKyösti Mälkki2014-04-291-11/+5
| | | | | | | | | | Change-Id: I11118a4fe1e05017349feae004f98a17bb02386b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5605 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* superio/winbond/w83627ehg: Convert romstage to generic componentEdward O'Callaghan2014-04-289-33/+16
| | | | | | | | | | | Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5589 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mainboard/tyan/s8226: Remove redundant sio headerEdward O'Callaghan2014-04-281-1/+0
| | | | | | | | Change-Id: I8d258c12d03e71fb525251104b4fa81596ad2187 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* superio/winbond/w83627dhg: Convert romstage to generic componentEdward O'Callaghan2014-04-288-24/+19
| | | | | | | | | | | | Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5588 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mainboard/asrock/e350m1: Avoid including early_serial.cEdward O'Callaghan2014-04-281-2/+3
| | | | | | | | | | | | | Use generic winbond romstage serial init symbols instead of model specific implementation. We do this on a case by case basis as some boards are ROMCC and so need to #include .c files. This is a step to migrate non-romcc boards to a more generic superio framework. Change-Id: I56f6d9ec77cd21a612cbbdb48634543f34a2e72c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5591 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* superio/winbond/*: Provide common romstage componentEdward O'Callaghan2014-04-284-0/+125
| | | | | | | | | | | Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I3e889c0305c012e7556a5dd348e7f1e1ba629a9d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5587 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* AMD: Add common header file for CAR setupKyösti Mälkki2014-04-2826-49/+39
| | | | | | | | Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4683 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* superio/fintek/*: Factor out generic romstage componentEdward O'Callaghan2014-04-2630-314/+69
| | | | | | | | | | | | | | | | | | | | | The romstage of Fintek Super I/O's is identical, leading to replication of essentially the same code prone to bitrot. Herein we consolidate the early pre-ram UART initialisation code into fintek/common, rather we leave the exceptions to be implemented under model/. More precisely we provide a well documented version of early_serial.c under fintek/common and select by way of Kconfig as a generic romstage component to Super I/O support. We leave future Super I/O's the option to implement `non-standard` initialisation code should such a (unlikely) need araise. A primary advantage is that new support for romstage serial is now trival to add. We also provide some Kconfig documentation while here. Change-Id: I3c62561558a62ece944a167ba302fb7076bba001 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5575 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* uart8250io: Fix build with DEBUG_SMIKyösti Mälkki2014-04-261-1/+2
| | | | | | | | Change-Id: I5110af348d22c0abc940f0922854fdd7e0c7e2e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.Edward O'Callaghan2014-04-261-2/+72
| | | | | | | | | | | | | | Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5198 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* lippert/hurricane-lx: Kconfig cleanupPatrick Georgi2014-04-261-3/+1
| | | | | | | | | | | A Kconfig option defined instead of selected that really comes from somewhere else. Change-Id: I8730d12ed053520b794655e943c93583c441f3f1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5542 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* superio/fintek/*: Fix header styleEdward O'Callaghan2014-04-2610-43/+40
| | | | | | | | | | | Remove some redundant includes. Fix repetitiveness in include guards and strip some misplaced tabs for whitespaces. Change-Id: I1f0bf6951cc6714f63e88b323754515fb02c089c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5572 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Rename coreboot_ram stage to ramstageFurquan Shaikh2014-04-2627-44/+44
| | | | | | | | | | | | | Rename coreboot_ram stage to ramstage. This is done in order to provide consistency with other stage names (bootblock, romstage) and to allow any Makefile rule generalization, required for patches to be submitted later. Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Get rid of HAVE_INIT_TIMER config optionFurquan Shaikh2014-04-2612-36/+4
| | | | | | | | | | | | | | | There is redundancy in terms of use of init_timer. We have a Kconfig option to decide whether a board has init_timer as well as we use a stub for init_timer in places where we do not have any init_timer defined. Thus, remove the Kconfig option. Henceforth, all boards that do not have init_timer functionality can include a stub_timer if required. Change-Id: I35d38ec686f4dc92861cf9248f9b540323cd98ae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5569 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* superio/ite/it8673f: Remove poor implementationEdward O'Callaghan2014-04-267-255/+0
| | | | | | | | | | | | Following the reasoning of: HASH superio/ite/it8705f: Remove poor implementation Change-Id: Ic0722116b84acf4f3c3ef4b18b961a56f0f50718 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5568 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* superio/ite/it8705f: Remove poor implementationEdward O'Callaghan2014-04-266-217/+0
| | | | | | | | | | | | | This super io support is poorly implemented and would not work for all boards since it hardcodes values. Since there are no users of it, remove for now pending a fresh reimplementation from scratch. Change-Id: I818a9f4d2ab106b989824e49cee49d79acd6041a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5566 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* superio/ite/it8716f: Rewrite from hardcoded base addrEdward O'Callaghan2014-04-269-79/+59
| | | | | | | | | | | | Following the same reasoning as: HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr Removing hard coded magics and expose sio pnp api in romstage. Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5565 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* superio/ite/it8721f: Rewrite from hardcoded base addrEdward O'Callaghan2014-04-266-54/+48
| | | | | | | | | | | | | | Rewrite early_serial.c implementation to honour a passed base address in device_t, removing any hard coding of values. We also expose early sio init functions as romstage symbols to avoid falsely #including "early_serial.c" in romstage.c of board support. Change-Id: I521b8f7cf85173345b90745c6f2ab66e25429f5d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5561 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mainboard/*: Remove DUMP_ACPI_TABLES from amd boardsEdward O'Callaghan2014-04-2645-1881/+0
| | | | | | | | | | | | | | | | | Dumping the ACPI tables in this way has limited use, is not likely to be used and is poorly implemented. There are much more sophisticated tools available on Linux for debugging ACPI as such this code is outside the scope of coreboots 'bring up the hardware only' philosophy. A more generic implemention could be done with hexdump() in coreboot proper following on from this cleanup. Change-Id: Ifd3bfb76338609d18fcf7158d3c9a6d7c06c8847 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5530 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* usbdebug: Add BeagleBone BlackKyösti Mälkki2014-04-221-0/+5
| | | | | | | | | | | Avoid some confusion as the selection of "BeagleBone" is not compatible with the product "BeagleBone Black". Change-Id: If73f80565cd26d2b41db972b4474ab85b609c1ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4289 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* Drop drivers/generic/debugKyösti Mälkki2014-04-2237-637/+0
| | | | | | | | | | Not very popular nor useful nowadays. Change-Id: I3dc0f7aaf188950a43f5350d3a95669fbbdcfd94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4554 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* southbridge/hudson: Initialize ACPI IO ports separate of FADTAlexandru Gagniuc2014-04-212-16/+33
| | | | | | | | | | | | | | | | | The ACPI IO ports, and the respective SMI (for HAVE_SMI_HANDLER), were initialized when the FADT table was written. This works well on a cold boot, but the ACPI ports are not initialized on S3 resume, as ACPI tables are not written. This will not work on S3 resume if the default ports are not what we set them, or if AGESA sets them to some other value. To solve this, move the port configuration to southbridge chip init. Change-Id: Ib4043f0fa5e20f08d320acd12ce84d4d789cd035 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5559 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
* hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18Alexandru Gagniuc2014-04-213-6/+7
| | | | | | | | | | | | | The PCIE PME pin from the APU is connected to GEVENT8, but the northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map accordingly. Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5556 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@gmail.com>
* hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11Alexandru Gagniuc2014-04-213-10/+22
| | | | | | | | | | | | | | Hudson ASL files assume the USB power event notifications are mapped to GPE 0xb. Since that GPE is not used on this board, map these events to GPE11. This GPE is already handled in ACPI via Method(_L0B). We adjust this method to also notify the XHCI controller at PCI 10:0. Change-Id: If33dd4bb5830820227f7c8b34594886cfae37282 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@gmail.com>
* AMD hudson and yangtze boards: Let mainboard declare power buttonAlexandru Gagniuc2014-04-2113-30/+64
| | | | | | | | | | | | | | | | | | The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and always had the wake source declared as GPE3. This is not the correct wake source for all boards. On some laptops declaring a wake source is not needed, as the wake mechanism is handled by the EC. Move the declaration of the power button to mainboard ASL files, and scope it as \_SB.PWRB . This also makes the naming consistent with the examples in the ACPI spec. The wake source for the PWRB of HP Pavilion M6 1035dx is removed, as it is incorrect. Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5546 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
* mainboard/asus/m5a88-v/devicetree.cb: Fix formattingEdward O'Callaghan2014-04-211-43/+43
| | | | | | | | | | | Strip incorrect comments pretaining to the superio, and replace spaces with tabs. Change-Id: Ib3f6094c552777552d0ec06e3236210ee2e7b05d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5562 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* hp/pavilion_m6_1035dx: Do not re-init EC and lid SMI on S3 resumeAlexandru Gagniuc2014-04-201-7/+12
| | | | | | | | | | | | | It's not needed, and puts the EC back into APM mode. The EC does not shut down during S3 sleep, so we don't need to re-initialize it. Lid SMI will have been disabled in the switch to ACPI mode, don't re-enable it. Change-Id: I2c06df140f63427dac32ae095d29e68f64135358 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5555 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* southbridge/hudson: Remove redundant definitions of ACPI IO portsAlexandru Gagniuc2014-04-203-12/+7
| | | | | | | | | | | The ACPI IO ports were defined twice, and used inconsistently. Only keep one of the definitions for consistency. Change-Id: If5744f9375fdaa97ceb9ba03dca8aa825eecf159 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5558 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* southbridge/amd/agesa/hudson: Refactor SPI controller driverAlexandru Gagniuc2014-04-201-19/+50
| | | | | | | | | | | | The SPI controller driver used numerical offsets to access SPI registers, making it unreadable without the datasheet. Use less magic and more #defines to improve readability. Change-Id: I8a1f11645cfce027e5df7a41a98c70249695889e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5557 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* hp/pavilion_m6_1035dx: Suspend/resume on lid close/open with ACPIAlexandru Gagniuc2014-04-203-0/+28
| | | | | | | | | | | | | | | | This patch completes ACPI support for the lid switch. The lid SCI now notifies the OSPM of the status change when the lid is closed or opened, allowing system to suspend. The wake source is also declares, and the system wakes when the lid is opened. The system resumes successfully, but the display still does not come back on. Change-Id: I803c4fc64e15f8d1a90791ec246af66604646d8b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5549 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* hp/pavilion_m6_1035dx: Add GEVENT to GPE SCI mapping tableAlexandru Gagniuc2014-04-202-1/+12
| | | | | | | | | | | | Each GEVENT pins can be mapped to a specific GPE via the SCI map. The default mapping is not appropriate for this laptop, so use the AGESA functionality to map currently known events. Change-Id: Ifa50bf000cfc8e77a6a4d84752f89838f165f7a0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5548 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* hp/pavilion_m6_1035dx: Move GEVENT/GPE definitions to common fileAlexandru Gagniuc2014-04-203-6/+25
| | | | | | | | | | | | These definitions were scattered in a couple of files, and we risk scattering them all over the place. Provide a common file for these definitions. Change-Id: I1fe99e5097cf10a349661f3b2ae2377f5cdd6103 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5547 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* Move MAX_PHYSICAL_CPUS to AMD k8 and fam10Kyösti Mälkki2014-04-203-7/+8
| | | | | | | | | | This was always AMD-only and it was never properly used with AGESA. Change-Id: Ifb461ee845e442f6cf90aca52470cfb66e862bfc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5540 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUSKyösti Mälkki2014-04-2013-76/+41
| | | | | | | | | | | | | | | | | | | | | | | | Following boards use cimx/sb700: amd/dinar supermicro/h8qgi supermicro/h8scm tyan/s8226 Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0. There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1). Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0. Together with documented 4-bit restriction for APIC ID field, this APIC ID programming matches with MP tables and ACPI tables. I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which we do not have in the tree. Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5539 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD AGESA cimx/sb800: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUSKyösti Mälkki2014-04-2010-72/+5
| | | | | | | | | | | All boards had APIC_ID_OFFSET=0 and MAX_PHYSICAL_CPUS=1. Change-Id: I6f08ea6de92a2af79fb3a99c5edd942b3a321c43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5538 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* amd/torpedo: Remove unused Kconfig optionsKyösti Mälkki2014-04-201-12/+0
| | | | | | | | | | These are not used with cimx/sb900 vendorcode. Change-Id: I489ee80c739b31edac649491497162c65316996e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5537 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD cimx sb700/sb800/sb900: Fix NODE_PCI and use of MAX_PHYSICAL_CPUSKyösti Mälkki2014-04-203-15/+3
| | | | | | | | | | | | | | Match the definition of NODE_PCI() with get_node_pci(), so romstage and ramstage agree of the PCI BDFs for nodes. Note that all board have CONFIG_CDB = 0x18 and the maximum for nodes = 8, so we always have (CONFIG_CDB + x) < 32. Change-Id: I676ee53a65ef5b1243df2c5889577dd987c8fc9c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* mainboard: New port Packard Bell LM85.Vladimir Serbinenko2014-04-2025-0/+2626
| | | | | | | | Change-Id: I8c1548470c605d06825fe35579879e806bf33542 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5271 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
* drivers/elog: Fix implicit function declaration issueEdward O'Callaghan2014-04-202-1/+5
| | | | | | | | | | | | Fix compilation. Relying on the pre-processor to condition an if statement will lead to warnings of implicitly defined functions. To solve this dilemma add symbols to resolve to at compile time. Change-Id: Id0117528c5579cc1dec750a8a17a76fab4314b3f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5504 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* rmodule: add subsections to linker scriptAaron Durbin2014-04-191-1/+4
| | | | | | | | | | | | | Depending on the compiler options, subsections of the form of .section.subsection could be generated. Therefore, include those subsections for .bss, .sbss, and .data. Change-Id: I80dd64d8c62e7bc449ee2bbc0a22a941777e2ea6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5407 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* hp/pavilion_m6_1035dx: Implement MB.LIDS ACPI methodAlexandru Gagniuc2014-04-191-1/+4
| | | | | | | | Change-Id: I654ca745f7404b86aa25fb2e696751d616d0ca03 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5517 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* hp/pavilion_m6_1035dx: Implement ACPI for wireless toggle hotkeyAlexandru Gagniuc2014-04-191-1/+4
| | | | | | | | Change-Id: I2e9ab68263648af8c9d46999e960f0a0711b61d7 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5516 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* ec/compal/ene932: Update to use coreboot EC-mainboard APIAlexandru Gagniuc2014-04-196-29/+83
| | | | | | | | | | | | | | This patch implements a simple interface between the EC and mainboard ASL code. This interface does not rely on the preprocessor, and prevents name conflicts by scoping the interface methods. As this interface is documented on the coreboot wiki, an in-tree documentation is not provided. Change-Id: If0b09be4f5e17cc444539a30f0186590fa0b72b5 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5515 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
* hp/pavilion_m6_1035dx: Rename "LID0" ACPI object to "LID"Alexandru Gagniuc2014-04-191-1/+1
| | | | | | | | | | | There is only one lid switch, so it does not make sense to number it. This naming is also consistent with the examples in the ACPI spec. Change-Id: Ida0a4a89ca03b2aad4fc77e52996e86332d370cd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5545 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* hp/pavilion_m6_1035dx: Shutdown when lid is closed on non-ACPI OSAlexandru Gagniuc2014-04-183-0/+14
| | | | | | | | | | | | This is handled by generating an SMI when GEVENT22 goes low. This pin is driven by the EC when the lid opens or closes. This SMI is disabled when switching to ACPI mode, so ACPI OSes are not affected. Change-Id: I38193572bf0416fd642002dba94c19257f0f6f5b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/171 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
* southbridge/hudson: Compile refactored SMI setup utilities in SMMAlexandru Gagniuc2014-04-185-53/+96
| | | | | | | | | | | | | | Refactor hudson_enable_gevent_smi() to allow configuring the interrupt mode and trigger level. Move the utilities which are useful in SMM to a separate file that is included in both ramstage and SMM. This is useful for SMI handlers which need to enable or disable GEVENT SMIs on-the-fly. A follow-up patch makes use of this infrastructure. Change-Id: Ifa4c300c00c178b18d7280690cfc4b8367c669b8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/170 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
* util/cbfstool: Fix "Bad segment type 53534220 Could not load payload".Wei Hu2014-04-181-1/+1
| | | | | | | | | | | | The magic number mismatch was introduced by commit a8a133 (Add section header parsing and use it in the mk-payload step). Change-Id: I73b0adb969816e9d130f19f48e175c57124e2f3a Signed-off-by: Wei Hu <wei@aristanetworks.com> Reviewed-on: http://review.coreboot.org/5528 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* hp/pavilion_m6_1035dx: Shutdown on low battery with non-ACPI OSAlexandru Gagniuc2014-04-181-4/+22
| | | | | | | | | | | | | | | | | Intercept the low battery SMI from the EC, and shut down the system immediately. The EC only sends this SMI when the OS did not enable ACPI mode, so ACPI OSes are not affected by this. On the other hand, payloads such as GRUB or SeaBIOS will experience the shutdown. This behavior is helpful for protecting the battery, for example, when the OS fails to boot and we are stuck in the payload. The low battery SMI is triggered at 10% charge, at which point the risk of cell degradation exists. Change-Id: I4c6c1a4feed8576cbdbb1945768de0805a1f5e42 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
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