diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram.inc | 8 | ||||
| -rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram_disable.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 8 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram_disable.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 8 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram_disable.c | 2 | ||||
| -rw-r--r-- | src/cpu/via/model_c7/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/x86/Kconfig | 1 |
8 files changed, 29 insertions, 3 deletions
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index a216aa3..dec09fe 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -114,7 +114,13 @@ clear_mtrrs: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE +#else +#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE +#endif + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx diff --git a/src/cpu/intel/model_106cx/cache_as_ram_disable.c b/src/cpu/intel/model_106cx/cache_as_ram_disable.c index 7808d56..d52bf0b 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram_disable.c +++ b/src/cpu/intel/model_106cx/cache_as_ram_disable.c @@ -25,6 +25,7 @@ void stage1_main(unsigned long bist) { unsigned int cpu_reset = 0; +#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK #if CONFIG_USE_FALLBACK_IMAGE == 1 /* Is this a deliberate reset by the bios */ if (bios_reset_detected() && last_boot_normal()) { @@ -46,6 +47,7 @@ void stage1_main(unsigned long bist) ); fallback_image: #endif +#endif real_main(bist); diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 9623dc4..28d5100 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -104,7 +104,13 @@ clear_mtrrs: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE +#else +#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE +#endif + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c index a22978e..fcdd3f2 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c +++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c @@ -27,6 +27,7 @@ void stage1_main(unsigned long bist) { unsigned int cpu_reset = 0; +#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK #if CONFIG_USE_FALLBACK_IMAGE == 1 /* Is this a deliberate reset by the bios */ if (bios_reset_detected() && last_boot_normal()) { @@ -48,6 +49,7 @@ void stage1_main(unsigned long bist) ); fallback_image: #endif +#endif real_main(bist); diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 5082a2e..a664da2 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -111,7 +111,13 @@ clear_mtrrs: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE +#else +#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE +#endif + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx diff --git a/src/cpu/intel/model_6fx/cache_as_ram_disable.c b/src/cpu/intel/model_6fx/cache_as_ram_disable.c index a22978e..fcdd3f2 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram_disable.c +++ b/src/cpu/intel/model_6fx/cache_as_ram_disable.c @@ -27,6 +27,7 @@ void stage1_main(unsigned long bist) { unsigned int cpu_reset = 0; +#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK #if CONFIG_USE_FALLBACK_IMAGE == 1 /* Is this a deliberate reset by the bios */ if (bios_reset_detected() && last_boot_normal()) { @@ -48,6 +49,7 @@ void stage1_main(unsigned long bist) ); fallback_image: #endif +#endif real_main(bist); diff --git a/src/cpu/via/model_c7/Kconfig b/src/cpu/via/model_c7/Kconfig index 22daaf4..8a2fe88 100644 --- a/src/cpu/via/model_c7/Kconfig +++ b/src/cpu/via/model_c7/Kconfig @@ -1,2 +1,3 @@ config CPU_VIA_C7 bool + select UDELAY_TSC diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index a3b9330..59f27de 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -8,6 +8,7 @@ config WAIT_BEFORE_CPUS_INIT config UDELAY_IO bool + default y if !UDELAY_LAPIC && !UDELAY_TSC default n config UDELAY_LAPIC |
