Rename coreboot_ram stage to ramstage

Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.

Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

24 files changed, 40 insertions, 40 deletions

diff --git a/src/Kconfig b/src/Kconfig
index e1d2e7a..6356b19 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -166,7 +166,7 @@ config INCLUDE_CONFIG_FILE
 	    Name                           Offset     Type         Size
 	    cmos_layout.bin                0x0        cmos layout  1159
 	    fallback/romstage              0x4c0      stage        339756
-	    fallback/coreboot_ram          0x53440    stage        186664
+	    fallback/ramstage          0x53440    stage        186664
 	    fallback/payload               0x80dc0    payload      51526
 	    config                         0x8d740    raw          3324
 	    (empty)                        0x8e480    null         3610440
diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc
index f0adc0a..6395b0c 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/armv7/Makefile.inc
@@ -65,10 +65,10 @@ $(obj)/coreboot.pre: $(CBFSTOOL)
 	mv $(obj)/coreboot.rom $@
 endif
 
-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE)
+$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 	cp $(obj)/coreboot.pre $@.tmp
-	$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG)
+	$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG)
 ifeq ($(CONFIG_PAYLOAD_NONE),y)
 	@printf "    PAYLOAD    none (as specified by user)\n"
 endif
@@ -117,17 +117,17 @@ $(stages_o): $(stages_c) $(obj)/config.h
 
 
 ################################################################################
-# Build the coreboot_ram (stage 2)
+# Build the ramstage (stage 2)
 
-$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/armv7/coreboot_ram.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/armv7/ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-	$(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/coreboot_ram.ld
+	$(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/ramstage.ld
 else
-	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/coreboot_ram.ld $<
+	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/ramstage.ld $<
 endif
 
-$(objgenerated)/coreboot_ram.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME)
+$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
 	$(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group
diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/ramstage.ld
index 452d2d7..42090f4 100644
--- a/src/arch/armv7/coreboot_ram.ld
+++ b/src/arch/armv7/ramstage.ld
@@ -16,7 +16,7 @@
 /*
  *	Written by Johan Rydberg, based on work by Daniel Kahlin.
  *      Rewritten by Eric Biederman
- *  2005.12 yhlu add coreboot_ram cross the vga font buffer handling
+ *  2005.12 yhlu add ramstage cross the vga font buffer handling
  */
 
 /* We use ELF as output format. So that we can debug the code in some form. */
diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld
index 459f714..0203efb 100644
--- a/src/arch/armv7/romstage.ld
+++ b/src/arch/armv7/romstage.ld
@@ -16,7 +16,7 @@
 /*
  *	Written by Johan Rydberg, based on work by Daniel Kahlin.
  *      Rewritten by Eric Biederman
- *  2005.12 yhlu add coreboot_ram cross the vga font buffer handling
+ *  2005.12 yhlu add ramstage cross the vga font buffer handling
  */
 
 /* We use ELF as output format. So that we can debug the code in some form. */
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index f986c3b..db8e500 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -99,10 +99,10 @@ $(REFCODE_BLOB): $(RMODTOOL)
 	$(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@
 endif
 
-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB)
+$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 	cp $(obj)/coreboot.pre $@.tmp
-	$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG)
+	$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG)
 ifeq ($(CONFIG_PAYLOAD_NONE),y)
 	@printf "    PAYLOAD    none (as specified by user)\n"
 endif
@@ -205,31 +205,31 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
 	mv $@.tmp $@
 
 ################################################################################
-# Build the coreboot_ram (stage 2)
+# Build the ramstage (stage 2)
 
 ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-$(eval $(call rmodule_link,$(objcbfs)/coreboot_ram.debug, $(objgenerated)/coreboot_ram.o, $(CONFIG_HEAP_SIZE)))
+$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE)))
 
 # The rmodule_link defintion creates an elf file with .rmod extension.
-$(objcbfs)/coreboot_ram.elf: $(objcbfs)/coreboot_ram.debug.rmod
+$(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
 else
 
-$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/x86/ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-	$(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/coreboot_ram.ld
+	$(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld
 else
-	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $<
+	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/ramstage.ld $<
 endif
 
 endif
 
-$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $$(ramstage-libs)
+$(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
 	$(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) --end-group
diff --git a/src/arch/x86/coreboot_ram.ld b/src/arch/x86/ramstage.ld
index 1d1143c..1c8e8dc 100644
--- a/src/arch/x86/coreboot_ram.ld
+++ b/src/arch/x86/ramstage.ld
@@ -16,7 +16,7 @@
 /*
  *	Written by Johan Rydberg, based on work by Daniel Kahlin.
  *      Rewritten by Eric Biederman
- *  2005.12 yhlu add coreboot_ram cross the vga font buffer handling
+ *  2005.12 yhlu add ramstage cross the vga font buffer handling
  */
 
 /* We use ELF as output format. So that we can debug the code in some form. */
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index 24533c7..7776ae7 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -36,7 +36,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
 #if CONFIG_DCACHE_RAM_SIZE > 0x8000
 	wrmsr(MTRRfix4K_C0000_MSR, msr);
 #endif
-	/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
+	/* disable fixed mtrr from now on, it will be enabled by ramstage again*/
 
 	msr = rdmsr(SYSCFG_MSR);
 	msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index f74f915..9712785 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -153,7 +153,7 @@ cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused)))
 
 	set_sysinfo_in_ram(1); // So other core0 could start to train mem
 
-	/*copy and execute coreboot_ram */
+	/*copy and execute ramstage */
 	copy_and_run();
 	/* We will not return */
 
diff --git a/src/cpu/amd/geode_lx/msrinit.c b/src/cpu/amd/geode_lx/msrinit.c
index 1118250..84fa548 100644
--- a/src/cpu/amd/geode_lx/msrinit.c
+++ b/src/cpu/amd/geode_lx/msrinit.c
@@ -42,11 +42,11 @@ static const msrinit_t msr_table[] =
 
 	/* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory.
 	 * It doesn't really matter in fact how much, however, because the only usage
-	 * of this extended memory will be to host the coreboot_ram stage at RAMBASE,
+	 * of this extended memory will be to host the ramstage stage at RAMBASE,
 	 * currently 1Mb.
 	 * These registers will be set to their correct value by the Northbridge init code.
 	 *
-	 * WARNING: if coreboot_ram could not be loaded, these registers are probably
+	 * WARNING: if ramstage could not be loaded, these registers are probably
 	 * incorrectly set here. You may comment the following two lines and set RAMBASE
 	 * to 0x4000 to revert to the previous behavior for LX-boards.
 	 */
diff --git a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc
index a269fb9..cc35060 100644
--- a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc
@@ -162,7 +162,7 @@ _clear_mtrrs_:
 	post_code(0x38)
 
 	/* Enable Write Back and Speculative Reads for the first MB
-	 * and coreboot_ram.
+	 * and ramstage.
 	 */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index b791881..e46a2ee 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -227,7 +227,7 @@ before_romstage:
 	post_code(0x38)
 
 	/* Enable Write Back and Speculative Reads for the first MB
-	 * and coreboot_ram.
+	 * and ramstage.
 	 */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 887d92b..1a19707 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -239,7 +239,7 @@ before_romstage:
 	post_code(0x38)
 
 	/* Enable Write Back and Speculative Reads for the first MB
-	 * and coreboot_ram.
+	 * and ramstage.
 	 */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c
index 814c5f1..9354738 100644
--- a/src/cpu/x86/pae/pgtbl.c
+++ b/src/cpu/x86/pae/pgtbl.c
@@ -1,5 +1,5 @@
 /*
-	2005.12 yhlu add coreboot_ram cross the vga font buffer handling
+	2005.12 yhlu add ramstage cross the vga font buffer handling
 */
 
 #include <console/console.h>
diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c
index be2be82..71eb22c 100644
--- a/src/lib/loaders/load_and_run_ramstage.c
+++ b/src/lib/loaders/load_and_run_ramstage.c
@@ -36,7 +36,7 @@ static const struct ramstage_loader_ops *loaders[] = {
 	&cbfs_ramstage_loader,
 };
 
-static const char *ramstage_name = CONFIG_CBFS_PREFIX "/coreboot_ram";
+static const char *ramstage_name = CONFIG_CBFS_PREFIX "/ramstage";
 static const uint32_t ramstage_id = CBMEM_ID_RAMSTAGE;
 
 static void
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index fe5c29f..84323ce 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -34,7 +34,7 @@ SECTIONS
 
 		/* The driver sections are to allow linking coreboot's
 		 * ramstage with the rmodule linker. Any changes made in
-		 * coreboot_ram.ld should be made here as well. */
+		 * ramstage.ld should be made here as well. */
 		pci_drivers = . ;
 		*(.rodata.pci_driver)
 		epci_drivers = . ;
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index feff03e..8e9e0de 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -29,7 +29,7 @@
 #include <bootmem.h>
 #include <payload_loader.h>
 
-/* from coreboot_ram.ld: */
+/* from ramstage.ld: */
 extern unsigned char _ram_seg;
 extern unsigned char _eram_seg;
 
@@ -418,7 +418,7 @@ static int load_self_segments(
 				/* Zero the extra bytes */
 				memset(middle, 0, end - middle);
 			}
-			/* Copy the data that's outside the area that shadows coreboot_ram */
+			/* Copy the data that's outside the area that shadows ramstage */
 			printk(BIOS_DEBUG, "dest %p, end %p, bouncebuffer %lx\n", dest, end, bounce_buffer);
 			if ((unsigned long)end > bounce_buffer) {
 				if ((unsigned long)dest < bounce_buffer) {
diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c
index 199842b..6a32c56 100644
--- a/src/mainboard/cubietech/cubieboard/romstage.c
+++ b/src/mainboard/cubietech/cubieboard/romstage.c
@@ -87,7 +87,7 @@ void main(void)
 		a1x_set_cpu_clock(384);
 	}
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
 	printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
 
 	stage_exit(entry);
diff --git a/src/mainboard/emulation/qemu-armv7/romstage.c b/src/mainboard/emulation/qemu-armv7/romstage.c
index 4a16436..00dfecd 100644
--- a/src/mainboard/emulation/qemu-armv7/romstage.c
+++ b/src/mainboard/emulation/qemu-armv7/romstage.c
@@ -23,7 +23,7 @@ void main(void)
 
 	console_init();
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
 
 	stage_exit(entry);
 }
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index b74c27f..c971d0c 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -274,7 +274,7 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
 	simple_spi_test();
 	stage_exit(entry);
 }
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index d45b861..3a8b5e8 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -186,6 +186,6 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
 	stage_exit(entry);
 }
diff --git a/src/mainboard/ti/beaglebone/romstage.c b/src/mainboard/ti/beaglebone/romstage.c
index e66a3dd..5dce23d 100644
--- a/src/mainboard/ti/beaglebone/romstage.c
+++ b/src/mainboard/ti/beaglebone/romstage.c
@@ -32,7 +32,7 @@ void main(void)
 	console_init();
 	printk(BIOS_INFO, "Hello from romstage.\n");
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
 	printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
 
 	stage_exit(entry);
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index aef2ad6..6e71b4e 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1033,7 +1033,7 @@ struct nodes_info_t {
 	u32 up_planes; // down planes will be [up_planes, planes)
 } __attribute__((packed));
 
-/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/
+/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/
 #if !CONFIG_AMDMCT
 
 //#define MEM_CS_COPY 1
diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
index e5bcdcb..a4943bd 100644
--- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c
+++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
@@ -80,7 +80,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
  *     pci1234[0] will record the south bridge link and bus range
  *     pci1234[i] will record HT chain i.
  *
- * For example, on the Tyan S2885 coreboot_ram will put the AMD8151 chain (HT
+ * For example, on the Tyan S2885 ramstage will put the AMD8151 chain (HT
  * link 0) into the register 0xE0, and the AMD8131/8111 HT chain into the
  * register 0xE4.
  *
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index 60f7abb..9dee295 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -177,7 +177,7 @@ static void bcm5785_early_setup(void)
         byte |= (1<<0); // SATA enable
         pci_write_config8(dev, 0x84, byte);
 
-// WDT and cf9 for later in coreboot_ram to call hard_reset
+// WDT and cf9 for later in ramstage to call hard_reset
         bcm5785_enable_wdt_port_cf9();
 
         bcm5785_enable_msg();