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| author | Sven Schnelle <svens@stackframe.org> | 2011-10-23 16:35:01 +0200 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2011-10-25 19:20:34 +0200 |
| commit | 906f9ae784b8a593319c400cbcc5e555a29b4128 (patch) | |
| tree | 463270b06f0b8c73b36ec28290df3ece8ad8c224 /src/southbridge/intel/i82801gx/lpc.c | |
| parent | 54600970417fee0e87d3059f6e6ac0a59d829066 (diff) | |
| download | coreboot-staging-906f9ae784b8a593319c400cbcc5e555a29b4128.zip coreboot-staging-906f9ae784b8a593319c400cbcc5e555a29b4128.tar.gz | |
i82801gx: Add setting for C4onC3 mode
If this bit is set, ich7 will enter C4 mode if possible instead of
C3. See ich7 specification (LPC controller, Power management control
registers) for more details.
Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/i82801gx/lpc.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ab3c915..c6b76d3 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -243,6 +243,10 @@ static void i82801gx_power_options(device_t dev) reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only reg16 |= (1 << 5); // CPUSLP_EN Desktop only + + if (config->c4onc3_enable) + reg16 |= (1 << 7); + // another laptop wants this? // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only |
