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| author | Ed Swierk <eswierk@arastra.com> | 2008-04-30 18:29:35 +0000 |
|---|---|---|
| committer | Ed Swierk <eswierk@arastra.com> | 2008-04-30 18:29:35 +0000 |
| commit | a9a5f49d8f69ed131f902f04f651ac96bd6f80cc (patch) | |
| tree | a3ebdc6096885a74f221b2a6ab8d1b2d37c65528 /src/southbridge/intel/i3100 | |
| parent | e21f836e4e65dd60c369e40ee7a38b17ccb20e44 (diff) | |
| download | coreboot-staging-a9a5f49d8f69ed131f902f04f651ac96bd6f80cc.zip coreboot-staging-a9a5f49d8f69ed131f902f04f651ac96bd6f80cc.tar.gz | |
By default, the Intel 3100 LPC interface enables only I/O range 0x3f8
for both serial ports, making it challenging to use COM2 for the early
console.
Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i3100')
| -rw-r--r-- | src/southbridge/intel/i3100/i3100_early_lpc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/i3100/i3100_early_lpc.c b/src/southbridge/intel/i3100/i3100_early_lpc.c index 7afe8c1..97d2b7c 100644 --- a/src/southbridge/intel/i3100/i3100_early_lpc.c +++ b/src/southbridge/intel/i3100/i3100_early_lpc.c @@ -23,6 +23,7 @@ static void i3100_enable_superio(void) device_t dev = PCI_DEV(0x0, 0x1f, 0x0); /* Enable decoding of I/O locations for SuperIO devices */ + pci_write_config16(dev, 0x80, 0x0010); pci_write_config16(dev, 0x82, 0x340f); } |
