diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2008-08-03 10:35:06 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2008-08-03 10:35:06 +0000 |
commit | 912857ec6c0995281460260de8da9f19277eb2f3 (patch) | |
tree | b22605aafc05f54d624902d6810fb8db9b69ec73 /src/pc80 | |
parent | 87c938f139b14a2e0b7fbfa6476c3caaa953e968 (diff) | |
download | coreboot-staging-912857ec6c0995281460260de8da9f19277eb2f3.zip coreboot-staging-912857ec6c0995281460260de8da9f19277eb2f3.tar.gz |
fix lots of warnings for cache as ram builds (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/pc80')
-rw-r--r-- | src/pc80/serial.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/pc80/serial.c b/src/pc80/serial.c index f8005da..45e0ce0 100644 --- a/src/pc80/serial.c +++ b/src/pc80/serial.c @@ -91,8 +91,13 @@ static void uart_init(void) #endif outb(UART_LCS, TTYS0_BASE + UART_LCR); } + #else +/* CONFIG_USE_PRINTK_IN_CAR == 1 */ +#if CONFIG_USE_INIT == 0 #include "../lib/uart8250.c" +#endif + extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs); static void uart_init(void) { |