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author | Peter Stuge <peter@stuge.se> | 2009-10-01 22:34:18 +0000 |
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committer | Peter Stuge <peter@stuge.se> | 2009-10-01 22:34:18 +0000 |
commit | 4c5786b1f905aa90d788a12a3b8656d0f551a618 (patch) | |
tree | dfc8240d60a17fc7d697cf84e776bf44fddc8d04 /src/northbridge | |
parent | 9536c06d18d96682da21023e9c3a83d4b78d3b58 (diff) | |
download | coreboot-staging-4c5786b1f905aa90d788a12a3b8656d0f551a618.zip coreboot-staging-4c5786b1f905aa90d788a12a3b8656d0f551a618.tar.gz |
Add some trivial numbers for 945, and Core2 Duo E8200 Intel parts
Sorry, but I've forgotten where I found them. :\
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r-- | src/northbridge/intel/i945/udelay.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 3a96c79..965c890 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -44,6 +44,18 @@ static void udelay(u32 us) case 3: fsb = 667; break; + case 2: + fsb = 800; + break; + case 0: + fsb = 1067; + break; + case 4: + fsb = 1333; + break; + case 6: + fsb = 1600; + break; } msr = rdmsr(0x198); |