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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-01-16 17:53:38 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-01-16 17:53:38 +0000 |
| commit | 9fe4d797a37671a65053add3f7cca27397db0b9b (patch) | |
| tree | 5cabbdc8b6e7eb970891b55d1ea3727a4a71aca2 /src/mainboard/intel/eagleheights/mptable.c | |
| parent | 984e0f3a0c3a82339ef8afcf7f315f377e0c81fc (diff) | |
| download | coreboot-staging-9fe4d797a37671a65053add3f7cca27397db0b9b.zip coreboot-staging-9fe4d797a37671a65053add3f7cca27397db0b9b.tar.gz | |
coreboot used to have two different "APIs" for memory accesses:
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)
read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.
This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel/eagleheights/mptable.c')
| -rw-r--r-- | src/mainboard/intel/eagleheights/mptable.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c index 7f2ca35..ac72aa0 100644 --- a/src/mainboard/intel/eagleheights/mptable.c +++ b/src/mainboard/intel/eagleheights/mptable.c @@ -234,10 +234,10 @@ void *smp_write_config_table(void *v) /* PCIe Port B */ for(i = 0; i < 4; i++) { - pin = (readl(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F; + pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F; if(pin > 0) { pin -= 1; - route = PIRQ_A + ((readw(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07); + route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route); } } @@ -245,20 +245,20 @@ void *smp_write_config_table(void *v) /* USB 1.1 : device 29, function 0, 1 */ for(i = 0; i < 2; i++) { - pin = (readl(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F; + pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F; if(pin > 0) { pin -= 1; - route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07); + route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route); } } /* USB 2.0 : device 29, function 7 */ - pin = (readl(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F; + pin = (read32(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F; if(pin > 0) { pin -= 1; - route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07); + route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route); } @@ -267,10 +267,10 @@ void *smp_write_config_table(void *v) Performance counters : device 31 function 4 */ for(i = 2; i < 5; i++) { - pin = (readl(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F; + pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F; if(pin > 0) { pin -= 1; - route = PIRQ_A + ((readw(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07); + route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route); } } |
