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| author | Myles Watson <mylesgw@gmail.com> | 2009-10-16 16:32:57 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-10-16 16:32:57 +0000 |
| commit | 0f61a4fc98f135c0ed22c67ee3241bf5670a61e2 (patch) | |
| tree | b3867408477cdf8a3a2374f32d91b4f3936b7486 /src/mainboard/amd | |
| parent | 9969bdc4fb3d36a39ed9efb67ef0bf638a4e8e09 (diff) | |
| download | coreboot-staging-0f61a4fc98f135c0ed22c67ee3241bf5670a61e2.zip coreboot-staging-0f61a4fc98f135c0ed22c67ee3241bf5670a61e2.tar.gz | |
Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP to match CONFIG_RAMBASE.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
5 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah/Options.lb b/src/mainboard/amd/serengeti_cheetah/Options.lb index dc57feb..a20289d 100644 --- a/src/mainboard/amd/serengeti_cheetah/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah/Options.lb @@ -80,7 +80,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -107,7 +107,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/amd/serengeti_cheetah/apc_auto.c b/src/mainboard/amd/serengeti_cheetah/apc_auto.c index 5a173e0..c8723e6 100644 --- a/src/mainboard/amd/serengeti_cheetah/apc_auto.c +++ b/src/mainboard/amd/serengeti_cheetah/apc_auto.c @@ -75,7 +75,7 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index df024f5..8d59b6c 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -95,9 +95,9 @@ config AMD_UCODE_PATCH_FILE default "mc_patch_01000095.h" depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 -config LB_MEM_TOPK +config RAMTOP hex - default 0x4000 + default 0x1000000 depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 config HEAP_SIZE diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb index a5ba422..2d82dfd 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb @@ -98,7 +98,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_PCI_BUS_SEGN_BITS @@ -135,7 +135,7 @@ default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time. -default CONFIG_LB_MEM_TOPK=16384 +default CONFIG_RAMTOP=16384*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c index fbb8c14..69e3ffb 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c @@ -74,7 +74,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; |
