diff options
author | Stefan Reinauer <stepan@openbios.org> | 2004-04-13 10:46:15 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2004-04-13 10:46:15 +0000 |
commit | 7ffd67bda4e67b43337dab9df2467cdda2789e29 (patch) | |
tree | cbaa1e6a0d917e1398a880dbb509d82991977b90 /src/drivers | |
parent | 35902425b8e3d346ab38112c95eecafe579f730f (diff) | |
download | coreboot-staging-7ffd67bda4e67b43337dab9df2467cdda2789e29.zip coreboot-staging-7ffd67bda4e67b43337dab9df2467cdda2789e29.tar.gz |
commit trident blade 3d driver
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/drivers')
-rw-r--r-- | src/drivers/trident/blade3d/Config.lb | 1 | ||||
-rw-r--r-- | src/drivers/trident/blade3d/blade3d.c | 1018 |
2 files changed, 1019 insertions, 0 deletions
diff --git a/src/drivers/trident/blade3d/Config.lb b/src/drivers/trident/blade3d/Config.lb new file mode 100644 index 0000000..0b2416d --- /dev/null +++ b/src/drivers/trident/blade3d/Config.lb @@ -0,0 +1 @@ +driver blade3d.o diff --git a/src/drivers/trident/blade3d/blade3d.c b/src/drivers/trident/blade3d/blade3d.c new file mode 100644 index 0000000..005aa8c --- /dev/null +++ b/src/drivers/trident/blade3d/blade3d.c @@ -0,0 +1,1018 @@ +/* + * firmware initialization code for Trident Blade3d graphics adapter + * written by Fuger Shen 2003-10-10 + * (C) 2003 XGI Technology Inc. + * This code is released under GPL with permission from XGI + */ +#include <delay.h> +#include <stdlib.h> +#include <string.h> +#include <arch/io.h> + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> + + +//----------------------------------------------------------------------------// +// init chip 9880 +// Fuger Shen 2003-10-10 +//----------------------------------------------------------------------------// + +#define inp inb +#define outp(port,val) outb(val, port) + +#define WORD unsigned int +#define BYTE unsigned char +#define DWORD unsigned long + +#define SGRAMTimg 0x27 +#define CHIPREV 0x3 //1,RA 2,RB,3,RC + +#define Port_SRX 0x3c4 +#define Port_CRX 0x3d4 +#define Port_GRX 0x3ce +#define Port_BRX 0x3c0 + +static BYTE Mem_Clk_Table[][2] = { + //For EDO, 3x5.2a.3:2=01 3x4.28.2:0 + 0x50, 0x46, //000, F_78 + 0xCF, 0x51, //001, F_81 = 81.011Mhz + 0x30, 0x83, //010, F_40 = 40.006Mhz + 0x1B, 0x43, //011, F_50 = 49.999MHz + 0x22, 0x43, //100, F_60 = 59.999MHz + 0x42, 0x46, //101, F_66 = 65.988MHz + 0x33, 0x44, //110, F_70 = 69.999Mhz + 0x22, 0x42, //111, F_75 = 74,999Mhz + //for SGRAM, 3x5.2a.3:2=1x + 0x3A, 0x05, //000, F_135 + 0x38, 0x05, //001, F_130 + 0x44, 0x44, //010, F_90 = 89.999MHz + 0x22, 0x04, //011, F_100=100.227MHz + 0x0E, 0x01, //100, F_105 + 0x3D, 0x07, //101, F_110=109.989Mhz + 0x22, 0x03, //110, F_120=119.999MHz + 0x36, 0x05, //111, F_125 +}; + + +typedef struct Reg_struct { + WORD rPort; + BYTE rIndex; + BYTE rValue; + BYTE rMask; +} Def_Reg_struct; + +typedef Def_Reg_struct* lpDef_Reg_struct; +// , *pDef_Reg_struct, far * lpDef_Reg_struct; + +static Def_Reg_struct Mode3_temp[] = { //mode3 temp + //port index value mask + {Port_CRX, 0x00, 0x5F, 0x00}, + {Port_CRX, 0x01, 0x4F, 0x00}, + {Port_CRX, 0x02, 0x50, 0x00}, + {Port_CRX, 0x03, 0x82, 0x00}, + {Port_CRX, 0x04, 0x55, 0x00}, + {Port_CRX, 0x05, 0x81, 0x00}, + {Port_CRX, 0x06, 0xBF, 0x00}, + {Port_CRX, 0x07, 0x1F, 0x00}, + {Port_CRX, 0x08, 0x00, 0x00}, + {Port_CRX, 0x09, 0xC7, 0x00}, + {Port_CRX, 0x0a, 0x06, 0x00}, + {Port_CRX, 0x0b, 0x07, 0x00}, + {Port_CRX, 0x0c, 0x00, 0x00}, + {Port_CRX, 0x0d, 0x00, 0x00}, + {Port_CRX, 0x0e, 0x00, 0x00}, + {Port_CRX, 0x0f, 0x00, 0x00}, + {Port_CRX, 0x10, 0x9C, 0x00}, + {Port_CRX, 0x11, 0x8E, 0x00}, + {Port_CRX, 0x12, 0x8F, 0x00}, + {Port_CRX, 0x13, 0x28, 0x00}, + {Port_CRX, 0x14, 0x1F, 0x00}, + {Port_CRX, 0x15, 0x96, 0x00}, + {Port_CRX, 0x16, 0xB9, 0x00}, + {Port_CRX, 0x17, 0xA3, 0x00}, + {Port_CRX, 0x18, 0xFF, 0x00}, +}; + +WORD Length_Mode3_temp = sizeof(Mode3_temp) / sizeof(Def_Reg_struct); + +Def_Reg_struct Mode3_reg[] = { //mode3 + //port index value mask + {Port_CRX, 0x00, 0x5F, 0x00}, //3d5 + {Port_CRX, 0x01, 0x4F, 0x00}, + {Port_CRX, 0x02, 0x50, 0x00}, + {Port_CRX, 0x03, 0x82, 0x00}, + {Port_CRX, 0x04, 0x55, 0x00}, + {Port_CRX, 0x05, 0x81, 0x00}, + {Port_CRX, 0x06, 0xBF, 0x00}, + {Port_CRX, 0x07, 0x1F, 0x00}, + {Port_CRX, 0x08, 0x00, 0x00}, + {Port_CRX, 0x09, 0x4F, 0x00}, + {Port_CRX, 0x0a, 0x0D, 0x00}, + {Port_CRX, 0x0b, 0x0E, 0x00}, + {Port_CRX, 0x0c, 0x00, 0x00}, + {Port_CRX, 0x0d, 0x00, 0x00}, + {Port_CRX, 0x0e, 0x00, 0x00}, + {Port_CRX, 0x0f, 0x00, 0x00}, + {Port_CRX, 0x10, 0x9C, 0x00}, + {Port_CRX, 0x11, 0x8E, 0x00}, + {Port_CRX, 0x12, 0x8F, 0x00}, + {Port_CRX, 0x13, 0x28, 0x00}, + {Port_CRX, 0x14, 0x1F, 0x00}, + {Port_CRX, 0x15, 0x96, 0x00}, + {Port_CRX, 0x16, 0xB9, 0x00}, + {Port_CRX, 0x17, 0xA3, 0x00}, + {Port_CRX, 0x18, 0xFF, 0x00}, + + //brx + {Port_BRX, 0x00, 0x00, 0x00}, + {Port_BRX, 0x01, 0x01, 0x00}, + {Port_BRX, 0x02, 0x02, 0x00}, + {Port_BRX, 0x03, 0x03, 0x00}, + {Port_BRX, 0x04, 0x04, 0x00}, + {Port_BRX, 0x05, 0x05, 0x00}, + {Port_BRX, 0x06, 0x14, 0x00}, + {Port_BRX, 0x07, 0x07, 0x00}, + {Port_BRX, 0x08, 0x38, 0x00}, + {Port_BRX, 0x09, 0x39, 0x00}, + {Port_BRX, 0x0a, 0x3A, 0x00}, + {Port_BRX, 0x0b, 0x3B, 0x00}, + {Port_BRX, 0x0c, 0x3C, 0x00}, + {Port_BRX, 0x0d, 0x3D, 0x00}, + {Port_BRX, 0x0e, 0x3E, 0x00}, + {Port_BRX, 0x0f, 0x3F, 0x00}, + {Port_BRX, 0x10, 0x0C, 0x00}, + {Port_BRX, 0x11, 0x00, 0x00}, + {Port_BRX, 0x12, 0x0F, 0x00}, + {Port_BRX, 0x13, 0x08, 0x00}, + {Port_BRX, 0x14, 0x00, 0x00}, + + {Port_SRX, 0x00, 0x03, 0x00}, + {Port_SRX, 0x01, 0x00, 0x00}, + {Port_SRX, 0x02, 0x03, 0x00}, + {Port_SRX, 0x03, 0x00, 0x00}, + {Port_SRX, 0x04, 0x02, 0x00}, + {Port_SRX, 0x18, 0xa6, 0x00}, //VCLK + {Port_SRX, 0x19, 0xc9, 0x00}, + {Port_SRX, 0x0D, 0x20, 0x00}, + {Port_SRX, 0x12, 0x11, 0x00}, + + {Port_CRX, 0x19, 0x4a, 0x00}, + //{Port_CRX, 0x20, 0x20, 0x00}, + //{Port_CRX, 0x23, 0x00, 0x00}, + //{Port_CRX, 0x1E, 0x89, 0x00}, + {Port_CRX, 0x21, 0xce, 0x00}, + //{Port_CRX, 0x25, 0x07, 0x00}, + //{Port_CRX, 0x27, 0x08, 0x00}, + //{Port_CRX, 0x2B, 0x00, 0x00}, + //{Port_CRX, 0x29, 0x04, 0x00}, + //{Port_CRX, 0x2F, 0x22, 0x00}, + {Port_CRX, 0x37, 0x81, 0x00}, + //{Port_CRX, 0x38, 0x00, 0x00}, + //{Port_CRX, 0x3b, 0x01, 0x00}, + {Port_CRX, 0x56, 0x00, 0x00}, + {Port_CRX, 0x57, 0x54, 0x00}, + + {Port_GRX, 0x05, 0x10, 0x00}, + {Port_GRX, 0x06, 0x0e, 0x00}, // + {Port_GRX, 0x0F, 0x20, 0x00}, + //{Port_GRX, 0x31, 0x06, 0x00}, + //{Port_GRX, 0x33, 0x30, 0x00}, + //{Port_GRX, 0x52, 0x10, 0x00}, +}; + +static WORD Length_Mode3_reg = sizeof(Mode3_reg) / sizeof(Def_Reg_struct); + +static Def_Reg_struct Init_reg[] = { + //port index value mask + {Port_GRX, 0x25, 0x00, 0x00}, + {Port_GRX, 0x21, 0x00, 0x00}, + {Port_GRX, 0x22, 0x00, 0x00}, + {Port_GRX, 0x26, 0x08, 0x00}, + {Port_GRX, 0x27, 0x00, 0x00}, + {Port_GRX, 0x28, 0xFF, 0x00}, + {Port_GRX, 0x29, 0x00, 0x00}, + {Port_GRX, 0x2A, 0x00, 0x00}, + {Port_GRX, 0x2C, 0x06, 0x00}, + {Port_GRX, 0x2E, 0x00, 0x00}, + {Port_GRX, 0x2F, 0x00, 0x00}, + {Port_GRX, 0x20, 0x80, 0x00}, + + {Port_SRX, 0x24, 0x0F, 0x00}, + {Port_SRX, 0x37, 0x30, 0x00}, + {Port_SRX, 0x38, 0x04, 0x00}, + + {Port_GRX, 0x23, 0x00, 0x00}, + {Port_GRX, 0x33, 0x20, 0x00}, + {Port_GRX, 0x30, 0x00, 0x00}, + // + {Port_GRX, 0x28, 0x18, 0x00}, + + {Port_CRX, 0x0F, 0x20, 0x40}, + {Port_CRX, 0x1F, 0x00, 0x00}, + {Port_CRX, 0x20, 0x30, 0x00}, + {Port_CRX, 0x23, 0x10, 0x00}, + {Port_CRX, 0x25, 0x86, 0x00}, + {Port_CRX, 0x2F, 0x1F, 0x00}, + {Port_CRX, 0x30, 0x0F, 0x00}, + {Port_CRX, 0x33, 0x00, 0x00}, + {Port_CRX, 0x38, 0x10, 0x00}, + {Port_CRX, 0x39, 0x00, 0x00}, + {Port_CRX, 0x5E, 0x00, 0x00}, + {Port_CRX, 0x29, 0x04, 0x00}, + + {Port_GRX, 0x5C, 0x00, 0x80}, + {Port_GRX, 0x62, 0x00, 0x08}, + + {Port_SRX, 0x20, 0x04, 0x00}, + {Port_GRX, 0x2F, 0x23, 0x00}, + {Port_SRX, 0x0B, 0x00, 0x00}, + {Port_SRX, 0x0D, 0x28, 0x00}, +}; + +static WORD Length_Init_reg = sizeof(Init_reg) / sizeof(Def_Reg_struct); + +static BYTE C8x16_Char[][8] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //;0 + 0x00, 0x00, 0x7E, 0x81, 0xA5, 0x81, 0x81, 0xBD, + 0x99, 0x81, 0x81, 0x7E, 0x00, 0x00, 0x00, 0x00, //;1 + 0x00, 0x00, 0x7E, 0xFF, 0xDB, 0xFF, 0xFF, 0xC3, + 0xE7, 0xFF, 0xFF, 0x7E, 0x00, 0x00, 0x00, 0x00, //;2 + 0x00, 0x00, 0x00, 0x00, 0x6C, 0xFE, 0xFE, 0xFE, + 0xFE, 0x7C, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, //;3 + 0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x7C, 0xFE, + 0x7C, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, //;4 + 0x00, 0x00, 0x00, 0x18, 0x3C, 0x3C, 0xE7, 0xE7, + 0xE7, 0x99, 0x18, 0x3C, 0x00, 0x00, 0x00, 0x00, //;5 + 0x00, 0x00, 0x00, 0x18, 0x3C, 0x7E, 0xFF, 0xFF, + 0x7E, 0x18, 0x18, 0x3C, 0x00, 0x00, 0x00, 0x00, //;6 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x3C, + 0x3C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //;7 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE7, 0xC3, + 0xC3, 0xE7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, //;8 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x66, 0x42, + 0x42, 0x66, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, //;9 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC3, 0x99, 0xBD, + 0xBD, 0x99, 0xC3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, ////10 + 0x00, 0x00, 0x1E, 0x0E, 0x1A, 0x32, 0x78, 0xCC, + 0xCC, 0xCC, 0xCC, 0x78, 0x00, 0x00, 0x00, 0x00, //11 + 0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x66, 0x3C, + 0x18, 0x7E, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, //12 + 0x00, 0x00, 0x3F, 0x33, 0x3F, 0x30, 0x30, 0x30, + 0x30, 0x70, 0xF0, 0xE0, 0x00, 0x00, 0x00, 0x00, //13 + 0x00, 0x00, 0x7F, 0x63, 0x7F, 0x63, 0x63, 0x63, + 0x63, 0x67, 0xE7, 0xE6, 0xC0, 0x00, 0x00, 0x00, //14 + 0x00, 0x00, 0x00, 0x18, 0x18, 0xDB, 0x3C, 0xE7, + 0x3C, 0xDB, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, //15 + 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFE, 0xF8, + 0xF0, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, //16 + 0x00, 0x02, 0x06, 0x0E, 0x1E, 0x3E, 0xFE, 0x3E, + 0x1E, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, //17 + 0x00, 0x00, 0x18, 0x3C, 0x7E, 0x18, 0x18, 0x18, + 0x18, 0x7E, 0x3C, 0x18, 0x00, 0x00, 0x00, 0x00, //18 + 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, + 0x66, 0x00, 0x66, 0x66, 0x00, 0x00, 0x00, 0x00, //19 + 0x00, 0x00, 0x7F, 0xDB, 0xDB, 0xDB, 0x7B, 0x1B, + 0x1B, 0x1B, 0x1B, 0x1B, 0x00, 0x00, 0x00, 0x00, //20 + 0x00, 0x7C, 0xC6, 0x60, 0x38, 0x6C, 0xC6, 0xC6, + 0x6C, 0x38, 0x0C, 0xC6, 0x7C, 0x00, 0x00, 0x00, //21 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xFE, 0xFE, 0xFE, 0xFE, 0x00, 0x00, 0x00, 0x00, //22 + 0x00, 0x00, 0x18, 0x3C, 0x7E, 0x18, 0x18, 0x18, + 0x18, 0x7E, 0x3C, 0x18, 0x7E, 0x00, 0x00, 0x00, //23 + 0x00, 0x00, 0x18, 0x3C, 0x7E, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, //24 + 0x00, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x7E, 0x3C, 0x18, 0x00, 0x00, 0x00, 0x00, //25 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x0C, 0xFE, + 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //26 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x60, 0xFE, + 0x60, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //27 + 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xC0, 0xC0, + 0xC0, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //28 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x6C, 0xFE, + 0x6C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //29 + 0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x38, 0x7C, + 0x7C, 0xFE, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, //30 + 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x7C, 0x7C, + 0x38, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, //31 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //32 + 0x00, 0x00, 0x18, 0x3C, 0x3C, 0x3C, 0x18, 0x18, + 0x18, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, //33 + 0x00, 0x66, 0x66, 0x66, 0x24, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //34 + 0x00, 0x00, 0x00, 0x6C, 0x6C, 0xFE, 0x6C, 0x6C, + 0x6C, 0xFE, 0x6C, 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0x76, 0x00, 0x00, 0x00, 0x00, //224 + 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xC6, 0xDC, 0xC6, + 0xC3, 0xC3, 0xC3, 0xCE, 0x00, 0x00, 0x00, 0x00, //225 + 0x00, 0x00, 0xFE, 0xC6, 0xC6, 0xC0, 0xC0, 0xC0, + 0xC0, 0xC0, 0xC0, 0xC0, 0x00, 0x00, 0x00, 0x00, //226 + 0x00, 0x00, 0x00, 0x00, 0x80, 0xFE, 0x6C, 0x6C, + 0x6C, 0x6C, 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00, //227 + 0x00, 0x00, 0x00, 0xFE, 0xC6, 0x60, 0x30, 0x18, + 0x30, 0x60, 0xC6, 0xFE, 0x00, 0x00, 0x00, 0x00, //228 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0xD8, 0xD8, + 0xD8, 0xD8, 0xD8, 0x70, 0x00, 0x00, 0x00, 0x00, //229 + 0x00, 0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, + 0x66, 0x7C, 0x60, 0x60, 0xC0, 0x00, 0x00, 0x00, //230 + 0x00, 0x00, 0x00, 0x00, 0x76, 0xDC, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, //231 + 0x00, 0x00, 0x00, 0x7E, 0x18, 0x3C, 0x66, 0x66, + 0x66, 0x3C, 0x18, 0x7E, 0x00, 0x00, 0x00, 0x00, //232 + 0x00, 0x00, 0x00, 0x38, 0x6C, 0xC6, 0xC6, 0xFE, + 0xC6, 0xC6, 0x6C, 0x38, 0x00, 0x00, 0x00, 0x00, //233 + 0x00, 0x00, 0x38, 0x6C, 0xC6, 0xC6, 0xC6, 0x6C, + 0x6C, 0x6C, 0x6C, 0xEE, 0x00, 0x00, 0x00, 0x00, //234 + 0x00, 0x00, 0x1E, 0x30, 0x18, 0x0C, 0x3E, 0x66, + 0x66, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, 0x00, //235 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0xDB, 0xDB, + 0xDB, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //236 + 0x00, 0x00, 0x00, 0x03, 0x06, 0x7E, 0xCF, 0xDB, + 0xF3, 0x7E, 0x60, 0xC0, 0x00, 0x00, 0x00, 0x00, //237 + 0x00, 0x00, 0x1C, 0x30, 0x60, 0x60, 0x7C, 0x60, + 0x60, 0x60, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x00, //238 + 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xC6, 0xC6, + 0xC6, 0xC6, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00, //239 + 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFE, + 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, //240 + 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x7E, 0x18, + 0x18, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, //241 + 0x00, 0x00, 0x00, 0x30, 0x18, 0x0C, 0x06, 0x0C, + 0x18, 0x30, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, //242 + 0x00, 0x00, 0x00, 0x0C, 0x18, 0x30, 0x60, 0x30, + 0x18, 0x0C, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, //243 + 0x00, 0x00, 0x0E, 0x1B, 0x1B, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, //244 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0xD8, 0xD8, 0xD8, 0x70, 0x00, 0x00, 0x00, 0x00, //245 + 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x7E, + 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, //246 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x76, 0xDC, 0x00, + 0x76, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //247 + 0x00, 0x38, 0x6C, 0x6C, 0x38, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //248 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, + 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //249 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //250 + 0x00, 0x0F, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0xEC, + 0x6C, 0x6C, 0x3C, 0x1C, 0x00, 0x00, 0x00, 0x00, //251 + 0x00, 0xD8, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //252 + 0x00, 0x70, 0x98, 0x30, 0x60, 0xC8, 0xF8, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //253 + 0x00, 0x00, 0x00, 0x00, 0x7C, 0x7C, 0x7C, 0x7C, + 0x7C, 0x7C, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, //254 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //255 +}; + +void config_OEM_regs(void); +void unprotect_reg(void); +void reprotect_reg(void); +void set_memCLK(BYTE mem_Type, BYTE mem_MD); +void init_SGRAM(void); +void config_video_memory(void); +void set_video_mode(void); +void clear_MEM(void); +void set_font(void); + +static int init9880(void) +{ + unprotect_reg(); + + //if use SDRAM + //outp(Port_CRX, 0x2a); + //outp(Port_CRX+1, (inp(Port_CRX+1) & ~0x0c) | 0x08); + //disable other card + + //enable VGA + outp(0x3c3, 0x01); + outp(0x4e68, 0x08); + + outp(0x3c2, 0x23); + + //if chip revB + if (CHIPREV == 0x02) { + outp(Port_CRX, 0xc0); + outp(Port_CRX + 1, 0x00); + } + config_OEM_regs(); + init_SGRAM(); + //config_video_memory(); + set_video_mode(); + reprotect_reg(); + //screen on + outp(Port_SRX, 0x01); + outp(Port_SRX + 1, inp(Port_SRX + 1) & ~0x20); +} + +static void config_OEM_regs(void) +{ + BYTE CRX_2A, Old_value; + BYTE mem_Type; + BYTE mem_MD; + WORD i; + + lpDef_Reg_struct lpMode3_temp; + lpDef_Reg_struct lpInit_reg; + lpMode3_temp = &Mode3_temp[0]; + lpInit_reg = &Init_reg[0]; + + outp(Port_GRX, 0x24); + outp(Port_GRX + 1, 0xe0); + //MCLK VCLK to 16 bit + outp(Port_CRX, 0xcf); + outp(Port_CRX + 1, inp(Port_CRX + 1) | 0x03); + //3c5.0e + //outp(Port_SRX, 0x3b); + //outp(Port_SRX+1, inp(Port_SRX+1) | 0x20); + // + outp(Port_CRX, 0x3b); + outp(Port_CRX + 1, inp(Port_CRX + 1) | 0x20); + // + outp(Port_CRX, 0x1a); + outp(Port_CRX + 1, inp(Port_CRX + 1) & 0x08); + // + outp(Port_CRX, 0x2a); + CRX_2A = inp(Port_CRX + 1); + outp(Port_CRX + 1, CRX_2A & ~0x20); + + mem_Type = (CRX_2A & ~0x20) & 0x08; + + outp(Port_GRX, 0x0f); + if (0x08 == mem_Type) + outp(Port_GRX + 1, inp(Port_GRX + 1) | 0x20); + else + outp(Port_GRX + 1, inp(Port_GRX + 1) & ~0x20); + + outp(Port_CRX, 0x28); + mem_MD = inp(Port_CRX + 1) & 0x07; + + set_memCLK(mem_Type, mem_MD); + delay(100); + + if (0x08 == mem_Type) { + outp(Port_CRX, 0x2e); + outp(Port_CRX + 1, 0x00); + delay(100); + outp(Port_CRX, 0x2d); + outp(Port_CRX + 1, 0x92); + } else { + outp(Port_CRX, 0x2d); + outp(Port_CRX + 1, 0x82); + } + + for (i = 0; i < Length_Mode3_temp; i++) { + outp(lpMode3_temp[i].rPort, lpMode3_temp[i].rIndex); + Old_value = inp(lpMode3_temp[i].rPort + 1); + outp(lpMode3_temp[i].rPort + 1, + lpMode3_temp[i].rValue | (Old_value & lpMode3_temp[i]. + rMask)); + } + //screen off + outp(Port_SRX, 0x01); + outp(Port_SRX + 1, inp(Port_SRX + 1) | 0x20); + + for (i = 0; i < Length_Init_reg; i++) { + outp(lpInit_reg[i].rPort, lpInit_reg[i].rIndex); + Old_value = inp(lpInit_reg[i].rPort + 1); + outp(lpInit_reg[i].rPort + 1, + lpInit_reg[i].rValue | (Old_value & lpInit_reg[i]. + rMask)); + } + delay(10); + init_SGRAM(); + + outp(Port_CRX, 0x1a); + if (0x08 == inp(Port_CRX + 1)) { + outp(Port_CRX, 0x20); + outp(Port_CRX + 1, inp(Port_CRX + 1) | 0x04); + } + +} //end config_OEM_reg + +//---------------------------------------------------------------------------// + +static void unprotect_reg(void) +{ + outp(Port_SRX, 0x11); + outp(Port_SRX + 1, 0x92); +} + +static void reprotect_reg(void) +{ + outp(Port_SRX, 0x11); + outp(Port_SRX + 1, 0x87); +} + +static void set_memCLK(BYTE mem_Type, BYTE mem_MD) +{ + BYTE Index; + + Index = ((mem_Type + mem_MD) << 0x01) & 0xf; + outp(Port_SRX, 0x16); + outp(Port_SRX + 1, Mem_Clk_Table[Index][0]); + outp(Port_SRX, 0x17); + outp(Port_SRX + 1, Mem_Clk_Table[Index][1]); + +} + +static void init_SGRAM(void) +{ + BYTE Temp, i; + + outp(Port_CRX, 0x2a); + if (inp(Port_CRX + 1) & 0x08) //SGRAM + { + outp(Port_CRX, 0x28); + if (inp(Port_CRX + 1) & 0x08) { + outp(Port_CRX, 0x1c); + outp(Port_CRX + 1, 0x7a); + } else { + outp(Port_CRX, 0x1c); + outp(Port_CRX + 1, 0x3a); + } + outp(Port_CRX, 0x1b); + outp(Port_CRX + 1, SGRAMTimg); + if (CHIPREV >= 0x03) { + outp(Port_CRX, 0x1a); + outp(Port_CRX + 1, inp(Port_CRX + 1) | 0x01); + } else { + outp(Port_CRX, 0x1a); + outp(Port_CRX + 1, 0x16); + outp(Port_CRX + 1, inp(Port_CRX + 1) | 0x16); + for (i = 0; i < 10; i++) { + outp(Port_CRX, 0x1c); + outp(Port_CRX + 1, + inp(Port_CRX + 1) | 0x40); + } + delay(100); + outp(Port_CRX, 0x1c); + Temp = (inp(Port_CRX + 1) | 0x20) & 0x3c; + outp(Port_CRX + 1, Temp); + outp(Port_CRX + 1, Temp & 0x08); + } + + } //SGRAM + +} + +static void config_video_memory(void) +{ +} + +static void set_video_mode(void) +{ + BYTE i; + BYTE Old_value; + lpDef_Reg_struct lpMode3_reg; + lpMode3_reg = &Mode3_reg[0]; + + outp(0x3c2, 0x67); + for (i = 0; i < Length_Mode3_reg; i++) { + if (lpMode3_reg[i].rPort == Port_BRX) { + inp(0x3DA); + delay(3); + outp(lpMode3_reg[i].rPort, lpMode3_reg[i].rIndex); + outp(lpMode3_reg[i].rPort, lpMode3_reg[i].rValue); + } else { + outp(lpMode3_reg[i].rPort, lpMode3_reg[i].rIndex); + Old_value = inp(lpMode3_reg[i].rPort + 1); + outp(lpMode3_reg[i].rPort + 1, + lpMode3_reg[i]. + rValue | (Old_value & lpMode3_reg[i].rMask)); + } + } + //set_font(); + //clear_MEM(); +} + +static void set_font(void) +{ + +} + +static void clear_MEM(void) +{ + //_fmemset(MK_FP(0xb800,0),0x720,0x4000); + __asm__("push %ax\n\t" + "push %cx\n\t" + "push %di\n\t" + "push %es\n\t" + "mov %ax, 0xb800\n\t" + "mov %es, %ax\n\t" + "mov %ax, 0x720\n\t" + "mov %cx, 0x4000\n\t" + "xor %di, %di\n\t" + "rep stosw\n\t" + "pop %es\n\t" + "pop %di\n\t" + "pop %cx\n\t" + "pop %ax\n\t" + ); +} + + +static void trident_blade3d_init(struct device *dev) +{ + init9880(); +} + +static struct device_operations trident_blade3d_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = trident_blade3d_init, + .scan_bus = 0, +}; + +static struct pci_driver trident_blade3d_driver __pci_driver = { + .ops = &trident_blade3d_ops, + .vendor = 0x1023, + .device = 0x9880, +}; + |