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author | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:17:25 +0000 |
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committer | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:17:25 +0000 |
commit | 6ca7636c8f52560e732cdd5b1c7829cda5aa2bde (patch) | |
tree | cc45ae7c4dea6e2c5338f52b4314106bf07023be /src/drivers | |
parent | b2ed53dd5669c2c3839633bd2b3b4af709a5b149 (diff) | |
download | coreboot-staging-6ca7636c8f52560e732cdd5b1c7829cda5aa2bde.zip coreboot-staging-6ca7636c8f52560e732cdd5b1c7829cda5aa2bde.tar.gz |
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
Creator: Yinghai Lu <yhlu@tyan.com>
cache_as_ram for AMD and some intel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/drivers')
-rw-r--r-- | src/drivers/generic/debug/debug_dev.c | 127 |
1 files changed, 120 insertions, 7 deletions
diff --git a/src/drivers/generic/debug/debug_dev.c b/src/drivers/generic/debug/debug_dev.c index 600b1fc..d5f9e62 100644 --- a/src/drivers/generic/debug/debug_dev.c +++ b/src/drivers/generic/debug/debug_dev.c @@ -76,26 +76,26 @@ static void print_cpuid() printk_debug("Reading msr: 0x%08x\n", index); msr = rdmsr(index); printk_debug("msr[0x%08x]: 0x%08x%08x\n", - index, msr.hi, msr.hi); + index, msr.hi, msr.lo); } } static void print_smbus_regs(struct device *dev) { int j; - printk_debug("smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link ); - printk_debug("%s", dev_path(dev)); + printk_debug("smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link); + printk_debug("%s", dev_path(dev)); for(j = 0; j < 256; j++) { int status; unsigned char byte; - if ((j & 0xf) == 0) { - printk_debug("\r\n%02x: ", j); - } status = smbus_read_byte(dev, j); if (status < 0) { - printk_debug("bad device status= %08x\r\n", status); + // printk_debug("bad device status= %08x\r\n", status); break; } + if ((j & 0xf) == 0) { + printk_debug("\r\n%02x: ", j); + } byte = status & 0xff; printk_debug("%02x ", byte); } @@ -125,9 +125,113 @@ static void print_smbus_regs_all(struct device *dev) } } } +static void print_msr_dualcore(void) +{ + msr_t msr; + unsigned index; + unsigned eax, ebx, ecx, edx; + index = 0x80000008; + printk_debug("calling cpuid 0x%08x\n", index); + asm volatile( + "cpuid" + : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) + : "a" (index) + ); + printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n", + index, eax, ebx, ecx, edx); + + printk_debug("core number %d\n", ecx & 0xff); + + index = 0xc001001f; + printk_debug("Reading msr: 0x%08x\n", index); + msr = rdmsr(index); + printk_debug("msr[0x%08x]: 0x%08x%08x bit 54 is %d\n", + index, msr.hi, msr.lo, (msr.hi>> (54-32)) & 1); +#if 0 + msr.hi |= (1<<(54-32)); + wrmsr(index, msr); + + msr = rdmsr(index); + printk_debug("msr[0x%08x]: 0x%08x%08x\n", + index, msr.hi, msr.lo); +#endif + +} + +static void print_cache_size(void) +{ + unsigned index; + unsigned int n, eax, ebx, ecx, edx; + + index = 0x80000000; + printk_debug("calling cpuid 0x%08x\n", index); + asm volatile( + "cpuid" + : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) + : "a" (index) + ); + n = eax; + + if (n >= 0x80000005) { + index = 0x80000005; + printk_debug("calling cpuid 0x%08x\n", index); + asm volatile( + "cpuid" + : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) + : "a" (index) + ); + printk_debug("CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", + edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); + } + + if (n >= 0x80000006) { + index = 0x80000006; + printk_debug("calling cpuid 0x%08x\n", index); + asm volatile( + "cpuid" + : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) + : "a" (index) + ); + printk_debug("CPU: L2 Cache: %dK (%d bytes/line)\n", + ecx >> 16, ecx & 0xFF); + } + +} + +struct tsc_struct { + unsigned lo; + unsigned hi; +}; +typedef struct tsc_struct tsc_t; + +static tsc_t rdtsc(void) +{ + tsc_t res; + asm volatile( + "rdtsc" + : "=a" (res.lo), "=d"(res.hi) /* outputs */ + ); + return res; +} + +static void print_tsc(void) { + + tsc_t tsc; + tsc = rdtsc(); + printk_debug("tsc: 0x%08x%08x\n", + tsc.hi, tsc.lo); + udelay(1); + tsc = rdtsc(); + printk_debug("tsc: 0x%08x%08x after udelay(1) \n", + tsc.hi, tsc.lo); + +} + static void debug_init(device_t dev) { +#if CONFIG_CHIP_NAME device_t parent; +#endif if (!dev->enabled) return; switch(dev->path.u.pnp.device) { @@ -155,6 +259,15 @@ static void debug_init(device_t dev) case 4: print_smbus_regs_all(&dev_root); break; + case 5: + print_msr_dualcore(); + break; + case 6: + print_cache_size(); + break; + case 7: + print_tsc(); + break; } } |