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| author | Patrick Georgi <patrick@georgi-clan.de> | 2011-10-31 17:07:52 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-11-01 19:06:23 +0100 |
| commit | 784544b934d67dc85ccfcf33e04ff148045836ad (patch) | |
| tree | 8f120ca06da0b126f09526d8814708b95ea6259f /src/cpu/amd/car | |
| parent | 36c04e8a5c54b100a505650218419e112ccc266e (diff) | |
| download | coreboot-staging-784544b934d67dc85ccfcf33e04ff148045836ad.zip coreboot-staging-784544b934d67dc85ccfcf33e04ff148045836ad.tar.gz | |
Remove XIP_ROM_BASE
The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).
Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/car')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index b9e02f3..955aec9 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -279,7 +279,7 @@ clear_fixed_var_mtrr_out: movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* Enable write base caching so we can do execute in place (XIP) * on the flash ROM. @@ -302,7 +302,7 @@ clear_fixed_var_mtrr_out: wbcache_post_fam10_setup: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRRdefType_MSR, %ecx |
