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authorarch import user (historical) <svn@openbios.org>2005-07-06 17:17:25 +0000
committerarch import user (historical) <svn@openbios.org>2005-07-06 17:17:25 +0000
commit6ca7636c8f52560e732cdd5b1c7829cda5aa2bde (patch)
treecc45ae7c4dea6e2c5338f52b4314106bf07023be /src/arch/i386/include/arch/io.h
parentb2ed53dd5669c2c3839633bd2b3b4af709a5b149 (diff)
downloadcoreboot-staging-6ca7636c8f52560e732cdd5b1c7829cda5aa2bde.zip
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Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/arch/i386/include/arch/io.h')
-rw-r--r--src/arch/i386/include/arch/io.h6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/i386/include/arch/io.h b/src/arch/i386/include/arch/io.h
index 4bd2f4a..07d0913 100644
--- a/src/arch/i386/include/arch/io.h
+++ b/src/arch/i386/include/arch/io.h
@@ -9,8 +9,7 @@
* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
* versions of the single-IO instructions (inb_p/inw_p/..).
*/
-
-#ifdef __ROMCC__
+#if defined( __ROMCC__ ) && !defined (__GNUC__)
static inline void outb(uint8_t value, uint16_t port)
{
__builtin_outb(value, port);
@@ -42,7 +41,6 @@ static inline uint32_t inl(uint16_t port)
{
return __builtin_inl(port);
}
-
#else
static inline void outb(uint8_t value, uint16_t port)
@@ -81,7 +79,7 @@ static inline uint32_t inl(uint16_t port)
return value;
}
-#endif /* __ROMCC__ */
+#endif /* __ROMCC__ && !__GNUC__*/
static inline void outsb(uint16_t port, const void *addr, unsigned long count)
{
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