diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-02-12 15:20:54 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-02-14 07:07:20 +0100 |
| commit | 0aa37c488bf785466e0db9897805ebf287af48eb (patch) | |
| tree | bbbdb3fd2cd6e9972d44df79e5c1232ba1928111 /documentation | |
| parent | 398e84c71a15b7db8c631bb5b17d1a1a60c91128 (diff) | |
| download | coreboot-staging-0aa37c488bf785466e0db9897805ebf287af48eb.zip coreboot-staging-0aa37c488bf785466e0db9897805ebf287af48eb.tar.gz | |
sconfig: rename lapic_cluster -> cpu_cluster
The name lapic_cluster is a bit misleading, since the construct is not local
APIC specific by concept. As implementations and hardware change, be more
generic about our naming. This will allow us to support non-x86 systems without
adding new keywords.
Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'documentation')
| -rw-r--r-- | documentation/Kconfig.tex | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/documentation/Kconfig.tex b/documentation/Kconfig.tex index 1739c05..6e59a7c 100644 --- a/documentation/Kconfig.tex +++ b/documentation/Kconfig.tex @@ -139,9 +139,9 @@ properly, as it defines topology and chips that can be defined no other way. Let's go through the tree. \begin{verbatim} chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device cpu_cluster 0 on chip cpu/amd/socket_F - device apic 0 on end + device lapic 0 on end end end \end{verbatim} @@ -153,11 +153,11 @@ somewhere, since it runs memory. What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the -CPU socket. So the tree is rooted at the northbridge, which has a link to an apic cluster, and then the CPU. The CPU contains +CPU socket. So the tree is rooted at the northbridge, which has a link to a CPU cluster, and then the CPU. The CPU contains its own APIC, and will define any parameters needed. In this case, we have a northbridge of type -{\it northbridge/amd/amdk8/root\_complex}, with its own apic\_cluster device which we turn on, +{\it northbridge/amd/amdk8/root\_complex}, with its own cpu\_cluster device which we turn on, which connects to a {\it cpu/amd/socket\_F}, -which has an apic, which is on. +which has a local apic, which is on. Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many |
