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| author | Siyuan Wang <wangsiyuanbuaa@gmail.com> | 2012-10-31 15:39:51 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-07 04:02:54 +0100 |
| commit | becacec022602ae1ab876c58d8ae69092327b9fe (patch) | |
| tree | 88006694e699965ce8b777a5708d86babaf5a66c /Makefile.inc | |
| parent | cf81b8294b95c13b27aa9f53ca8e958699b4290c (diff) | |
| download | coreboot-staging-becacec022602ae1ab876c58d8ae69092327b9fe.zip coreboot-staging-becacec022602ae1ab876c58d8ae69092327b9fe.tar.gz | |
AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU
Each G34 socket has two node. Previous lapic algorithm is written for
the CPU which has one node per socket. I test the code on h8qgi with
4 family 15 CPUs(8 cores per CPU). The topology is:
socket 0 --> Node 0, Node 1
socket 2 --> Node 2, Node 3
socket 1 --> Node 4, Node 5
socket 3 --> Node 6, Node 7
Each node has 4 cores.
I change the code according to this topology.
Change-Id: I45f242e0dfc61bd9b18afc952d7a0ad6a0fc3855
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1659
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'Makefile.inc')
0 files changed, 0 insertions, 0 deletions
