Eliminate special case id.inc/id.lds in favor of a configuration variable ID_SECTION_OFFSET

which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative)
where necessary (if romstraps get in the way).
For Kconfig, the special case is set per southbridge (as these define the necessity for this
workaround), for newconfig it's added to each single board.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

57 files changed, 140 insertions, 205 deletions

diff --git a/src/Kconfig b/src/Kconfig
index c2a56e1..6fe473c 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -467,3 +467,7 @@ config ENABLE_APIC_EXT_ID
 config WARNINGS_ARE_ERRORS
 	bool
 	default n
+
+config ID_SECTION_OFFSET
+	hex
+	default 0x10
diff --git a/src/arch/i386/lib/id.inc b/src/arch/i386/lib/id.inc
index 181ab63..9f402f8 100644
--- a/src/arch/i386/lib/id.inc
+++ b/src/arch/i386/lib/id.inc
@@ -6,9 +6,9 @@ vendor:
 	.asciz CONFIG_MAINBOARD_VENDOR
 part:		
 	.asciz CONFIG_MAINBOARD_PART_NUMBER
-.long __id_end + 0x10 - vendor  /* Reverse offset to the vendor id */
-.long __id_end + 0x10 - part    /* Reverse offset to the part number */
-.long CONFIG_ROM_SIZE           /* Size of this romimage */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor  /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - part    /* Reverse offset to the part number */
+.long CONFIG_ROM_SIZE                               /* Size of this romimage */
 	.globl __id_end
 
 __id_end:
diff --git a/src/arch/i386/lib/id.lds b/src/arch/i386/lib/id.lds
index 8f9149a..d646270 100644
--- a/src/arch/i386/lib/id.lds
+++ b/src/arch/i386/lib/id.lds
@@ -1,5 +1,5 @@
 SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start);
+	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}
diff --git a/src/config/Options.lb b/src/config/Options.lb
index 4d28bd5..2ed9b47 100644
--- a/src/config/Options.lb
+++ b/src/config/Options.lb
@@ -1132,3 +1132,8 @@ define CONFIG_PCIE_CONFIGSPACE_HOLE
 	comment "Leave a hole for PCIe config space in the device allocator"
 end
 
+define CONFIG_ID_SECTION_OFFSET
+	default 0x10
+	export always
+	comment "Offset of the .id section. Only needs to change if something like a romstrap is in the way"
+end
diff --git a/src/mainboard/Makefile.k8_ck804.inc b/src/mainboard/Makefile.k8_ck804.inc
index e412f8e..ad394fc 100644
--- a/src/mainboard/Makefile.k8_ck804.inc
+++ b/src/mainboard/Makefile.k8_ck804.inc
@@ -39,7 +39,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/ck804/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/ck804/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -47,7 +47,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/ck804/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/ck804/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
index 35e0965..5a17e34 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
@@ -113,6 +113,8 @@ uses CONFIG_AMDMCT
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_AMD_UCODE_PATCH_FILE
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -357,5 +359,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb
index b499514..374629c 100644
--- a/src/mainboard/asus/a8n_e/Config.lb
+++ b/src/mainboard/asus/a8n_e/Config.lb
@@ -78,8 +78,8 @@ else
 	end
 end
 # Include an ID string (for safe flashing).
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 # ROMSTRAP table for CK804.
 if CONFIG_HAVE_FAILOVER_BOOT
 	if CONFIG_USE_FAILOVER_IMAGE
diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb
index 02d4407..a03db4b 100644
--- a/src/mainboard/asus/a8n_e/Options.lb
+++ b/src/mainboard/asus/a8n_e/Options.lb
@@ -94,6 +94,7 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_ID_SECTION_OFFSET
 
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE
@@ -162,5 +163,6 @@ default CONFIG_TTYS0_LCS = 0x3
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
+default CONFIG_ID_SECTION_OFFSET = 0x80
 
 end
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
index 40a96f4..6cca586 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
@@ -113,8 +113,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/sis/sis966/id.inc
-ldscript /southbridge/sis/sis966/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc b/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc
index 1130d07..35c46f0 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc
@@ -33,14 +33,14 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/sis/sis966/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/sis/sis966/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
 
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
index 97a8a4c..252d588 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
@@ -115,6 +115,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -347,5 +349,6 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
 ### End Options.lb
 end
diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb
index cabb1b2..c84d73c 100644
--- a/src/mainboard/gigabyte/m57sli/Config.lb
+++ b/src/mainboard/gigabyte/m57sli/Config.lb
@@ -111,8 +111,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/gigabyte/m57sli/Makefile.inc b/src/mainboard/gigabyte/m57sli/Makefile.inc
index 12d966c..44fedbb 100644
--- a/src/mainboard/gigabyte/m57sli/Makefile.inc
+++ b/src/mainboard/gigabyte/m57sli/Makefile.inc
@@ -36,7 +36,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -44,7 +44,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
diff --git a/src/mainboard/gigabyte/m57sli/Options.lb b/src/mainboard/gigabyte/m57sli/Options.lb
index df828f7..3010a2a 100644
--- a/src/mainboard/gigabyte/m57sli/Options.lb
+++ b/src/mainboard/gigabyte/m57sli/Options.lb
@@ -116,6 +116,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 
 uses CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
+
+uses CONFIG_ID_SECTION_OFFSET
 ###
 ### Build options
 ###
@@ -356,5 +358,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb
index ce8565c..adc58a9 100644
--- a/src/mainboard/msi/ms7135/Config.lb
+++ b/src/mainboard/msi/ms7135/Config.lb
@@ -107,8 +107,8 @@ end
 ##
 ## Include an ID string (for safe flashing).
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
diff --git a/src/mainboard/msi/ms7135/Options.lb b/src/mainboard/msi/ms7135/Options.lb
index 2337734..b3b2b4b 100644
--- a/src/mainboard/msi/ms7135/Options.lb
+++ b/src/mainboard/msi/ms7135/Options.lb
@@ -99,6 +99,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ## ---> 512 Kbytes 
 default CONFIG_ROM_SIZE=(512*1024)
@@ -313,5 +315,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/msi/ms7260/Config.lb b/src/mainboard/msi/ms7260/Config.lb
index b460061..f420731 100644
--- a/src/mainboard/msi/ms7260/Config.lb
+++ b/src/mainboard/msi/ms7260/Config.lb
@@ -93,8 +93,8 @@ else
   end
 end
 
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 # ROMSTRAP table for MCP55.
 if CONFIG_HAVE_FAILOVER_BOOT
diff --git a/src/mainboard/msi/ms7260/Makefile.inc b/src/mainboard/msi/ms7260/Makefile.inc
index f10f36c..2baa947 100644
--- a/src/mainboard/msi/ms7260/Makefile.inc
+++ b/src/mainboard/msi/ms7260/Makefile.inc
@@ -33,14 +33,14 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
 
diff --git a/src/mainboard/msi/ms7260/Options.lb b/src/mainboard/msi/ms7260/Options.lb
index 54b62c1..1be372a 100644
--- a/src/mainboard/msi/ms7260/Options.lb
+++ b/src/mainboard/msi/ms7260/Options.lb
@@ -96,6 +96,7 @@ uses CONFIG_AP_CODE_IN_CAR
 uses CONFIG_MEM_TRAIN_SEQ
 uses CONFIG_WAIT_BEFORE_CPUS_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_ID_SECTION_OFFSET
 
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
@@ -182,5 +183,6 @@ default CONFIG_TTYS0_LCS = 0x3
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
+default CONFIG_ID_SECTION_OFFSET=0x80
 
 end
diff --git a/src/mainboard/msi/ms9282/Config.lb b/src/mainboard/msi/ms9282/Config.lb
index 8faf611..ec1211e 100644
--- a/src/mainboard/msi/ms9282/Config.lb
+++ b/src/mainboard/msi/ms9282/Config.lb
@@ -94,8 +94,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/msi/ms9282/Makefile.inc b/src/mainboard/msi/ms9282/Makefile.inc
index 510ee6f..d04e6f5 100644
--- a/src/mainboard/msi/ms9282/Makefile.inc
+++ b/src/mainboard/msi/ms9282/Makefile.inc
@@ -35,14 +35,14 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
 
diff --git a/src/mainboard/msi/ms9282/Options.lb b/src/mainboard/msi/ms9282/Options.lb
index 146cc21..ee8be01 100644
--- a/src/mainboard/msi/ms9282/Options.lb
+++ b/src/mainboard/msi/ms9282/Options.lb
@@ -99,6 +99,8 @@ uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes
 default CONFIG_ROM_SIZE=524288
@@ -303,5 +305,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/nvidia/l1_2pvv/Config.lb b/src/mainboard/nvidia/l1_2pvv/Config.lb
index 0b1bfb0..ba30037 100644
--- a/src/mainboard/nvidia/l1_2pvv/Config.lb
+++ b/src/mainboard/nvidia/l1_2pvv/Config.lb
@@ -141,8 +141,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/nvidia/l1_2pvv/Makefile.inc b/src/mainboard/nvidia/l1_2pvv/Makefile.inc
index 66cc3e6..ccb1094 100644
--- a/src/mainboard/nvidia/l1_2pvv/Makefile.inc
+++ b/src/mainboard/nvidia/l1_2pvv/Makefile.inc
@@ -33,7 +33,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
diff --git a/src/mainboard/nvidia/l1_2pvv/Options.lb b/src/mainboard/nvidia/l1_2pvv/Options.lb
index b7b445a..00efb92 100644
--- a/src/mainboard/nvidia/l1_2pvv/Options.lb
+++ b/src/mainboard/nvidia/l1_2pvv/Options.lb
@@ -113,6 +113,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -345,5 +347,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/sunw/ultra40/Config.lb b/src/mainboard/sunw/ultra40/Config.lb
index b00c2bc..2781be8 100644
--- a/src/mainboard/sunw/ultra40/Config.lb
+++ b/src/mainboard/sunw/ultra40/Config.lb
@@ -62,8 +62,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
diff --git a/src/mainboard/sunw/ultra40/Options.lb b/src/mainboard/sunw/ultra40/Options.lb
index c9d550e..e820fd0 100644
--- a/src/mainboard/sunw/ultra40/Options.lb
+++ b/src/mainboard/sunw/ultra40/Options.lb
@@ -69,6 +69,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes 
 #default CONFIG_ROM_SIZE=524288
@@ -272,5 +274,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/supermicro/h8dme/Config.lb b/src/mainboard/supermicro/h8dme/Config.lb
index 2141907..18cde51 100644
--- a/src/mainboard/supermicro/h8dme/Config.lb
+++ b/src/mainboard/supermicro/h8dme/Config.lb
@@ -108,8 +108,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/supermicro/h8dme/Makefile.inc b/src/mainboard/supermicro/h8dme/Makefile.inc
index 8075ba2..d53db01 100644
--- a/src/mainboard/supermicro/h8dme/Makefile.inc
+++ b/src/mainboard/supermicro/h8dme/Makefile.inc
@@ -34,7 +34,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -42,7 +42,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
diff --git a/src/mainboard/supermicro/h8dme/Options.lb b/src/mainboard/supermicro/h8dme/Options.lb
index 5a36135..85d8331 100644
--- a/src/mainboard/supermicro/h8dme/Options.lb
+++ b/src/mainboard/supermicro/h8dme/Options.lb
@@ -114,6 +114,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -347,5 +349,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/supermicro/h8dmr/Config.lb b/src/mainboard/supermicro/h8dmr/Config.lb
index cc95167..13db09a 100644
--- a/src/mainboard/supermicro/h8dmr/Config.lb
+++ b/src/mainboard/supermicro/h8dmr/Config.lb
@@ -110,8 +110,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/supermicro/h8dmr/Makefile.inc b/src/mainboard/supermicro/h8dmr/Makefile.inc
index 8b64208..5d5c44a 100644
--- a/src/mainboard/supermicro/h8dmr/Makefile.inc
+++ b/src/mainboard/supermicro/h8dmr/Makefile.inc
@@ -33,7 +33,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
diff --git a/src/mainboard/supermicro/h8dmr/Options.lb b/src/mainboard/supermicro/h8dmr/Options.lb
index 5e457d0..f0e9082 100644
--- a/src/mainboard/supermicro/h8dmr/Options.lb
+++ b/src/mainboard/supermicro/h8dmr/Options.lb
@@ -112,6 +112,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -345,5 +347,7 @@ default CONFIG_USE_FAILOVER_IMAGE=0
 default CONFIG_USE_FALLBACK_IMAGE=0
 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Config.lb b/src/mainboard/supermicro/h8dmr_fam10/Config.lb
index cd9dd54..fe2d1b6 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/Config.lb
+++ b/src/mainboard/supermicro/h8dmr_fam10/Config.lb
@@ -112,8 +112,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc b/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
index 8b64208..5d5c44a 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
+++ b/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
@@ -33,7 +33,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Options.lb b/src/mainboard/supermicro/h8dmr_fam10/Options.lb
index e2739a6..a7d3ca8 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/Options.lb
+++ b/src/mainboard/supermicro/h8dmr_fam10/Options.lb
@@ -115,6 +115,7 @@ uses CONFIG_AMDMCT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_AMD_UCODE_PATCH_FILE
+uses CONFIG_ID_SECTION_OFFSET
 
 ###
 ### Build options
@@ -356,5 +357,7 @@ default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 default CONFIG_USE_FAILOVER_IMAGE=0
 default CONFIG_USE_FALLBACK_IMAGE=0
 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
+
+default CONFIG_ID_SECTION_OFFSET=0x80
 ### End Options.lb
 end
diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb
index 53da12b..42627a3 100644
--- a/src/mainboard/tyan/s2891/Config.lb
+++ b/src/mainboard/tyan/s2891/Config.lb
@@ -77,8 +77,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb
index 63c5f93..a0ed35b 100644
--- a/src/mainboard/tyan/s2891/Options.lb
+++ b/src/mainboard/tyan/s2891/Options.lb
@@ -77,6 +77,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=512*1024
 
@@ -294,5 +296,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb
index 35328e5..3864558 100644
--- a/src/mainboard/tyan/s2892/Config.lb
+++ b/src/mainboard/tyan/s2892/Config.lb
@@ -78,8 +78,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb
index 89a897b..e3f1606 100644
--- a/src/mainboard/tyan/s2892/Options.lb
+++ b/src/mainboard/tyan/s2892/Options.lb
@@ -71,6 +71,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=1024*1024
 
@@ -282,5 +284,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb
index e4946de..1b7f808 100644
--- a/src/mainboard/tyan/s2895/Config.lb
+++ b/src/mainboard/tyan/s2895/Config.lb
@@ -90,8 +90,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb
index 864fc30..6659c9a 100644
--- a/src/mainboard/tyan/s2895/Options.lb
+++ b/src/mainboard/tyan/s2895/Options.lb
@@ -82,6 +82,8 @@ uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
 uses CONFIG_RAMTOP
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=1024*1024
 
@@ -303,5 +305,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/tyan/s2912/Config.lb b/src/mainboard/tyan/s2912/Config.lb
index 08f824b..35511f8 100644
--- a/src/mainboard/tyan/s2912/Config.lb
+++ b/src/mainboard/tyan/s2912/Config.lb
@@ -111,8 +111,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/tyan/s2912/Makefile.inc b/src/mainboard/tyan/s2912/Makefile.inc
index acfa14f..c21cdb3 100644
--- a/src/mainboard/tyan/s2912/Makefile.inc
+++ b/src/mainboard/tyan/s2912/Makefile.inc
@@ -33,7 +33,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
diff --git a/src/mainboard/tyan/s2912/Options.lb b/src/mainboard/tyan/s2912/Options.lb
index a8de386..52d8202 100644
--- a/src/mainboard/tyan/s2912/Options.lb
+++ b/src/mainboard/tyan/s2912/Options.lb
@@ -113,6 +113,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -347,5 +349,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb
index f3765f27..538abab 100644
--- a/src/mainboard/tyan/s2912_fam10/Config.lb
+++ b/src/mainboard/tyan/s2912_fam10/Config.lb
@@ -111,8 +111,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/tyan/s2912_fam10/Makefile.inc b/src/mainboard/tyan/s2912_fam10/Makefile.inc
index acfa14f..c21cdb3 100644
--- a/src/mainboard/tyan/s2912_fam10/Makefile.inc
+++ b/src/mainboard/tyan/s2912_fam10/Makefile.inc
@@ -33,7 +33,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb
index 0a73728..d9444d8 100644
--- a/src/mainboard/tyan/s2912_fam10/Options.lb
+++ b/src/mainboard/tyan/s2912_fam10/Options.lb
@@ -115,6 +115,7 @@ uses CONFIG_AMDMCT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_AMD_UCODE_PATCH_FILE
+uses CONFIG_ID_SECTION_OFFSET
 
 ###
 ### Build options
@@ -355,5 +356,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 92c8fba..810b5b8 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -3,3 +3,7 @@ config SOUTHBRIDGE_NVIDIA_CK804
 	select HAVE_HARD_RESET
 	select IOAPIC
 
+config ID_SECTION_OFFSET
+	hex
+	default 0x80 if SOUTHBRIDGE_NVIDIA_CK804
+
diff --git a/src/southbridge/nvidia/ck804/id.inc b/src/southbridge/nvidia/ck804/id.inc
deleted file mode 100644
index 3200a7d..0000000
--- a/src/southbridge/nvidia/ck804/id.inc
+++ /dev/null
@@ -1,15 +0,0 @@
-	.section ".id", "a", @progbits
-
-	.globl __id_start
-__id_start:
-vendor:
-	.asciz CONFIG_MAINBOARD_VENDOR
-part:
-	.asciz CONFIG_MAINBOARD_PART_NUMBER
-.long __id_end + 0x80 - vendor       /* Reverse offset to the vendor ID */
-.long __id_end + 0x80 - part         /* Reverse offset to the part number */
-.long CONFIG_ROM_SIZE                /* Size of this ROM image */
-	.globl __id_end
-
-__id_end:
-.previous
diff --git a/src/southbridge/nvidia/ck804/id.lds b/src/southbridge/nvidia/ck804/id.lds
deleted file mode 100644
index d95b9af..0000000
--- a/src/southbridge/nvidia/ck804/id.lds
+++ /dev/null
@@ -1,6 +0,0 @@
-SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
-	.id (.): {
-		*(.id)
-	}
-}
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index d0fc94b..96e2ebc 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -1,2 +1,6 @@
 config SOUTHBRIDGE_NVIDIA_MCP55
 	bool
+
+config ID_SECTION_OFFSET
+	hex
+	default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55
diff --git a/src/southbridge/nvidia/mcp55/id.inc b/src/southbridge/nvidia/mcp55/id.inc
deleted file mode 100644
index 7ea744c..0000000
--- a/src/southbridge/nvidia/mcp55/id.inc
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-	.section ".id", "a", @progbits
-
-	.globl __id_start
-__id_start:
-vendor:
-	.asciz CONFIG_MAINBOARD_VENDOR
-part:
-	.asciz CONFIG_MAINBOARD_PART_NUMBER
-.long __id_end + 0x80 - vendor  /* Reverse offset to the vendor id */
-.long __id_end + 0x80 - part    /* Reverse offset to the part number */
-.long CONFIG_ROM_SIZE           /* Size of this romimage */
-	.globl __id_end
-
-__id_end:
-.previous
diff --git a/src/southbridge/nvidia/mcp55/id.lds b/src/southbridge/nvidia/mcp55/id.lds
deleted file mode 100644
index 53215be..0000000
--- a/src/southbridge/nvidia/mcp55/id.lds
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
-	.id (.): {
-		*(.id)
-	}
-}
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index a61c5dd..3d87e67 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -1,2 +1,6 @@
 config SOUTHBRIDGE_SIS_SIS966
 	bool
+
+config ID_SECTION_OFFSET
+	hex
+	default 0x80 if SOUTHBRIDGE_SIS_SIS966
diff --git a/src/southbridge/sis/sis966/id.inc b/src/southbridge/sis/sis966/id.inc
deleted file mode 100644
index 7ea744c..0000000
--- a/src/southbridge/sis/sis966/id.inc
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-	.section ".id", "a", @progbits
-
-	.globl __id_start
-__id_start:
-vendor:
-	.asciz CONFIG_MAINBOARD_VENDOR
-part:
-	.asciz CONFIG_MAINBOARD_PART_NUMBER
-.long __id_end + 0x80 - vendor  /* Reverse offset to the vendor id */
-.long __id_end + 0x80 - part    /* Reverse offset to the part number */
-.long CONFIG_ROM_SIZE           /* Size of this romimage */
-	.globl __id_end
-
-__id_end:
-.previous
diff --git a/src/southbridge/sis/sis966/id.lds b/src/southbridge/sis/sis966/id.lds
deleted file mode 100644
index 53215be..0000000
--- a/src/southbridge/sis/sis966/id.lds
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
-	.id (.): {
-		*(.id)
-	}
-}