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| author | Richard Purdie <rpurdie@linux.intel.com> | 2010-08-27 15:14:24 +0100 |
|---|---|---|
| committer | Richard Purdie <rpurdie@linux.intel.com> | 2010-08-27 15:29:45 +0100 |
| commit | 29d6678fd546377459ef75cf54abeef5b969b5cf (patch) | |
| tree | 8edd65790e37a00d01c3f203f773fe4b5012db18 /meta/recipes-kernel/linux/linux-omap2-git/beagleboard | |
| parent | da49de6885ee1bc424e70bc02f21f6ab920efb55 (diff) | |
| download | ast2050-yocto-poky-29d6678fd546377459ef75cf54abeef5b969b5cf.zip ast2050-yocto-poky-29d6678fd546377459ef75cf54abeef5b969b5cf.tar.gz | |
Major layout change to the packages directory
Having one monolithic packages directory makes it hard to find things
and is generally overwhelming. This commit splits it into several
logical sections roughly based on function, recipes.txt gives more
information about the classifications used.
The opportunity is also used to switch from "packages" to "recipes"
as used in OpenEmbedded as the term "packages" can be confusing to
people and has many different meanings.
Not all recipes have been classified yet, this is just a first pass
at separating things out. Some packages are moved to meta-extras as
they're no longer actively used or maintained.
Signed-off-by: Richard Purdie <rpurdie@linux.intel.com>
Diffstat (limited to 'meta/recipes-kernel/linux/linux-omap2-git/beagleboard')
45 files changed, 81375 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch new file mode 100644 index 0000000..6e31ead --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch @@ -0,0 +1,55 @@ +From a1dbb6dd28e9815a307b87b8d96dcf371d6cfd58 Mon Sep 17 00:00:00 2001 +From: Jarkko Nikula <jarkko.nikula@nokia.com> +Date: Mon, 19 May 2008 13:24:41 +0300 +Subject: [PATCH] ASoC: OMAP: Add basic support for OMAP34xx in McBSP DAI driver + +This adds support for OMAP34xx McBSP port 1 and 2. + +Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com> +--- + sound/soc/omap/omap-mcbsp.c | 20 +++++++++++++++++++- + 1 files changed, 19 insertions(+), 1 deletions(-) + +diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c +index 40d87e6..8e6ec9d 100644 +--- a/sound/soc/omap/omap-mcbsp.c ++++ b/sound/soc/omap/omap-mcbsp.c +@@ -99,6 +99,21 @@ static const unsigned long omap2420_mcbsp_port[][2] = { + static const int omap2420_dma_reqs[][2] = {}; + static const unsigned long omap2420_mcbsp_port[][2] = {}; + #endif ++#if defined(CONFIG_ARCH_OMAP34XX) ++static const int omap34xx_dma_reqs[][2] = { ++ { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX }, ++ { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX }, ++}; ++static const unsigned long omap34xx_mcbsp_port[][2] = { ++ { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR2, ++ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR2 }, ++ { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR2, ++ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR2 }, ++}; ++#else ++static const int omap34xx_dma_reqs[][2] = {}; ++static const unsigned long omap34xx_mcbsp_port[][2] = {}; ++#endif + + static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream) + { +@@ -169,9 +184,12 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, + } else if (cpu_is_omap2420()) { + dma = omap2420_dma_reqs[bus_id][substream->stream]; + port = omap2420_mcbsp_port[bus_id][substream->stream]; ++ } else if (cpu_is_omap343x()) { ++ dma = omap34xx_dma_reqs[bus_id][substream->stream]; ++ port = omap34xx_mcbsp_port[bus_id][substream->stream]; + } else { + /* +- * TODO: Add support for 2430 and 3430 ++ * TODO: Add support for 2430 + */ + return -ENODEV; + } +-- +1.5.5.1 + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0001-omap3-cpuidle.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0001-omap3-cpuidle.patch new file mode 100644 index 0000000..cdc9447 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0001-omap3-cpuidle.patch @@ -0,0 +1,450 @@ +From: "Rajendra Nayak" <rnayak@ti.com> +To: <linux-omap@vger.kernel.org> +Subject: [PATCH 01/02] OMAP3 CPUidle driver +Date: Tue, 10 Jun 2008 12:39:00 +0530 + +This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver +before it queries the governor for the next state. + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> + +--- + arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++ + arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++ + arch/arm/mach-omap2/pm34xx.c | 5 + drivers/cpuidle/cpuidle.c | 10 + + 5 files changed, 359 insertions(+), 2 deletions(-) + +Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530 +@@ -20,7 +20,7 @@ obj-y += pm.o + obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o + obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o + obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o +-obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o ++obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o + obj-$(CONFIG_PM_DEBUG) += pm-debug.o + endif + +Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530 +@@ -0,0 +1,293 @@ ++/* ++ * linux/arch/arm/mach-omap2/cpuidle34xx.c ++ * ++ * OMAP3 CPU IDLE Routines ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Rajendra Nayak <rnayak@ti.com> ++ * ++ * Copyright (C) 2007 Texas Instruments, Inc. ++ * Karthik Dasu <karthik-dp@ti.com> ++ * ++ * Copyright (C) 2006 Nokia Corporation ++ * Tony Lindgren <tony@atomide.com> ++ * ++ * Copyright (C) 2005 Texas Instruments, Inc. ++ * Richard Woodruff <r-woodruff2@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/cpuidle.h> ++#include <asm/arch/pm.h> ++#include <asm/arch/prcm.h> ++#include <asm/arch/powerdomain.h> ++#include <asm/arch/clockdomain.h> ++#include <asm/arch/irqs.h> ++#include "cpuidle34xx.h" ++ ++#ifdef CONFIG_CPU_IDLE ++ ++struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; ++struct omap3_processor_cx current_cx_state; ++ ++static int omap3_idle_bm_check(void) ++{ ++ /* Check for omap3_fclks_active() here once available */ ++ return 0; ++} ++ ++/* omap3_enter_idle - Programs OMAP3 to enter the specified state. ++ * returns the total time during which the system was idle. ++ */ ++static int omap3_enter_idle(struct cpuidle_device *dev, ++ struct cpuidle_state *state) ++{ ++ struct omap3_processor_cx *cx = cpuidle_get_statedata(state); ++ struct timespec ts_preidle, ts_postidle, ts_idle; ++ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd; ++ int neon_pwrst; ++ ++ current_cx_state = *cx; ++ ++ if (cx->type == OMAP3_STATE_C0) { ++ /* Do nothing for C0, not even a wfi */ ++ return 0; ++ } ++ ++ /* Used to keep track of the total time in idle */ ++ getnstimeofday(&ts_preidle); ++ ++ mpu_pd = pwrdm_lookup("mpu_pwrdm"); ++ core_pd = pwrdm_lookup("core_pwrdm"); ++ per_pd = pwrdm_lookup("per_pwrdm"); ++ neon_pd = pwrdm_lookup("neon_pwrdm"); ++ ++ /* Reset previous power state registers */ ++ pwrdm_clear_all_prev_pwrst(mpu_pd); ++ pwrdm_clear_all_prev_pwrst(neon_pd); ++ pwrdm_clear_all_prev_pwrst(core_pd); ++ pwrdm_clear_all_prev_pwrst(per_pd); ++ ++ if (omap_irq_pending()) ++ return 0; ++ ++ neon_pwrst = pwrdm_read_pwrst(neon_pd); ++ ++ /* Program MPU/NEON to target state */ ++ if (cx->mpu_state < PWRDM_POWER_ON) { ++ if (neon_pwrst == PWRDM_POWER_ON) { ++ if (cx->mpu_state == PWRDM_POWER_RET) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET); ++ else if (cx->mpu_state == PWRDM_POWER_OFF) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF); ++ } ++ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state); ++ } ++ ++ /* Program CORE to target state */ ++ if (cx->core_state < PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(core_pd, cx->core_state); ++ ++ /* Execute ARM wfi */ ++ omap_sram_idle(); ++ ++ /* Program MPU/NEON to ON */ ++ if (cx->mpu_state < PWRDM_POWER_ON) { ++ if (neon_pwrst == PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON); ++ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON); ++ } ++ ++ if (cx->core_state < PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON); ++ ++ getnstimeofday(&ts_postidle); ++ ts_idle = timespec_sub(ts_postidle, ts_preidle); ++ return timespec_to_ns(&ts_idle); ++} ++ ++/* ++ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM ++ * ++ * This function checks for all the pre-requisites needed for OMAP3 to enter ++ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired ++ * C state. ++ */ ++static int omap3_enter_idle_bm(struct cpuidle_device *dev, ++ struct cpuidle_state *state) ++{ ++ struct cpuidle_state *new_state = NULL; ++ int i, j; ++ ++ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { ++ ++ /* Find current state in list */ ++ for (i = 0; i < OMAP3_MAX_STATES; i++) ++ if (state == &dev->states[i]) ++ break; ++ BUG_ON(i == OMAP3_MAX_STATES); ++ ++ /* Back up to non 'CHECK_BM' state */ ++ for (j = i - 1; j > 0; j--) { ++ struct cpuidle_state *s = &dev->states[j]; ++ ++ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) { ++ new_state = s; ++ break; ++ } ++ } ++ ++ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n", ++ __FUNCTION__, new_state->name, state->name); ++ } ++ ++ return omap3_enter_idle(dev, new_state ? : state); ++} ++ ++DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); ++ ++/* omap3_init_power_states - Initialises the OMAP3 specific C states. ++ * Below is the desciption of each C state. ++ * ++ C0 . System executing code ++ C1 . MPU WFI + Core active ++ C2 . MPU CSWR + Core active ++ C3 . MPU OFF + Core active ++ C4 . MPU CSWR + Core CSWR ++ C5 . MPU OFF + Core CSWR ++ C6 . MPU OFF + Core OFF ++ */ ++void omap_init_power_states(void) ++{ ++ /* C0 . System executing code */ ++ omap3_power_states[0].valid = 1; ++ omap3_power_states[0].type = OMAP3_STATE_C0; ++ omap3_power_states[0].sleep_latency = 0; ++ omap3_power_states[0].wakeup_latency = 0; ++ omap3_power_states[0].threshold = 0; ++ omap3_power_states[0].mpu_state = PWRDM_POWER_ON; ++ omap3_power_states[0].core_state = PWRDM_POWER_ON; ++ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_SHALLOW; ++ ++ /* C1 . MPU WFI + Core active */ ++ omap3_power_states[1].valid = 1; ++ omap3_power_states[1].type = OMAP3_STATE_C1; ++ omap3_power_states[1].sleep_latency = 10; ++ omap3_power_states[1].wakeup_latency = 10; ++ omap3_power_states[1].threshold = 30; ++ omap3_power_states[1].mpu_state = PWRDM_POWER_ON; ++ omap3_power_states[1].core_state = PWRDM_POWER_ON; ++ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_SHALLOW; ++ ++ /* C2 . MPU CSWR + Core active */ ++ omap3_power_states[2].valid = 1; ++ omap3_power_states[2].type = OMAP3_STATE_C2; ++ omap3_power_states[2].sleep_latency = 50; ++ omap3_power_states[2].wakeup_latency = 50; ++ omap3_power_states[2].threshold = 300; ++ omap3_power_states[2].mpu_state = PWRDM_POWER_RET; ++ omap3_power_states[2].core_state = PWRDM_POWER_ON; ++ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED; ++ ++ /* C3 . MPU OFF + Core active */ ++ omap3_power_states[3].valid = 0; ++ omap3_power_states[3].type = OMAP3_STATE_C3; ++ omap3_power_states[3].sleep_latency = 1500; ++ omap3_power_states[3].wakeup_latency = 1800; ++ omap3_power_states[3].threshold = 4000; ++ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[3].core_state = PWRDM_POWER_RET; ++ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED; ++ ++ /* C4 . MPU CSWR + Core CSWR*/ ++ omap3_power_states[4].valid = 1; ++ omap3_power_states[4].type = OMAP3_STATE_C4; ++ omap3_power_states[4].sleep_latency = 2500; ++ omap3_power_states[4].wakeup_latency = 7500; ++ omap3_power_states[4].threshold = 12000; ++ omap3_power_states[4].mpu_state = PWRDM_POWER_RET; ++ omap3_power_states[4].core_state = PWRDM_POWER_RET; ++ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; ++ ++ /* C5 . MPU OFF + Core CSWR */ ++ omap3_power_states[5].valid = 0; ++ omap3_power_states[5].type = OMAP3_STATE_C5; ++ omap3_power_states[5].sleep_latency = 3000; ++ omap3_power_states[5].wakeup_latency = 8500; ++ omap3_power_states[5].threshold = 15000; ++ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[5].core_state = PWRDM_POWER_RET; ++ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; ++ ++ /* C6 . MPU OFF + Core OFF */ ++ omap3_power_states[6].valid = 0; ++ omap3_power_states[6].type = OMAP3_STATE_C6; ++ omap3_power_states[6].sleep_latency = 10000; ++ omap3_power_states[6].wakeup_latency = 30000; ++ omap3_power_states[6].threshold = 300000; ++ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[6].core_state = PWRDM_POWER_OFF; ++ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM; ++} ++ ++struct cpuidle_driver omap3_idle_driver = { ++ .name = "omap3_idle", ++ .owner = THIS_MODULE, ++}; ++/* ++ * omap3_idle_init - Init routine for OMAP3 idle. ++ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w ++ * with the valid set of states. ++ */ ++int omap3_idle_init(void) ++{ ++ int i, count = 0; ++ struct omap3_processor_cx *cx; ++ struct cpuidle_state *state; ++ struct cpuidle_device *dev; ++ ++ omap_init_power_states(); ++ cpuidle_register_driver(&omap3_idle_driver); ++ ++ dev = &per_cpu(omap3_idle_dev, smp_processor_id()); ++ ++ for (i = 0; i < OMAP3_MAX_STATES; i++) { ++ cx = &omap3_power_states[i]; ++ state = &dev->states[count]; ++ ++ if (!cx->valid) ++ continue; ++ cpuidle_set_statedata(state, cx); ++ state->exit_latency = cx->sleep_latency + cx->wakeup_latency; ++ state->target_residency = cx->threshold; ++ state->flags = cx->flags; ++ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? ++ omap3_enter_idle_bm : omap3_enter_idle; ++ sprintf(state->name, "C%d", count+1); ++ count++; ++ } ++ ++ if (!count) ++ return -EINVAL; ++ dev->state_count = count; ++ ++ if (cpuidle_register_device(dev)) { ++ printk(KERN_ERR "%s: CPUidle register device failed\n", ++ __FUNCTION__); ++ return -EIO; ++ } ++ ++ return 0; ++} ++__initcall(omap3_idle_init); ++#endif /* CONFIG_CPU_IDLE */ +Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530 +@@ -0,0 +1,51 @@ ++/* ++ * linux/arch/arm/mach-omap2/cpuidle34xx.h ++ * ++ * OMAP3 cpuidle structure definitions ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Written by Rajendra Nayak <rnayak@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ * ++ * History: ++ * ++ */ ++ ++#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX ++#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX ++ ++#define OMAP3_MAX_STATES 7 ++#define OMAP3_STATE_C0 0 /* C0 - System executing code */ ++#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */ ++#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */ ++#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */ ++#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */ ++#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */ ++#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */ ++ ++extern void omap_sram_idle(void); ++extern int omap3_irq_pending(void); ++ ++struct omap3_processor_cx { ++ u8 valid; ++ u8 type; ++ u32 sleep_latency; ++ u32 wakeup_latency; ++ u32 mpu_state; ++ u32 core_state; ++ u32 threshold; ++ u32 flags; ++}; ++ ++void omap_init_power_states(void); ++int omap3_idle_init(void); ++ ++#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */ ++ +Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530 +@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle + return IRQ_HANDLED; + } + +-static void omap_sram_idle(void) ++void omap_sram_idle(void) + { + /* Variable to tell what needs to be saved and restored + * in omap_sram_idle*/ +@@ -156,6 +156,7 @@ static void omap_sram_idle(void) + + mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); + switch (mpu_next_state) { ++ case PWRDM_POWER_ON: + case PWRDM_POWER_RET: + /* No need to save context */ + save_state = 0; +@@ -386,7 +387,9 @@ int __init omap3_pm_init(void) + + prcm_setup_regs(); + ++#ifndef CONFIG_CPU_IDLE + pm_idle = omap3_pm_idle; ++#endif + + err1: + return ret; +Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c +=================================================================== +--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530 ++++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530 +@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void) + return; + } + ++#ifdef CONFIG_ARCH_OMAP3 ++ local_irq_disable(); ++ local_fiq_disable(); ++#endif ++ + /* ask the governor for the next state */ + next_state = cpuidle_curr_governor->select(dev); + if (need_resched()) +@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void) + target_state->time += (unsigned long long)dev->last_residency; + target_state->usage++; + ++#ifdef CONFIG_ARCH_OMAP3 ++ local_irq_enable(); ++ local_fiq_enable(); ++#endif ++ + /* give the governor an opportunity to reflect on the outcome */ + if (cpuidle_curr_governor->reflect) + cpuidle_curr_governor->reflect(dev); + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch new file mode 100644 index 0000000..17329be --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch @@ -0,0 +1,69 @@ +From 7a444ee080c5f1a62ac5042f1e7926622b3e1ce7 Mon Sep 17 00:00:00 2001 +From: Koen Kooi <koen@openembedded.org> +Date: Fri, 30 May 2008 13:43:36 +0200 +Subject: [PATCH] ARM: OMAP: omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver + +omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver + * on revision A5 and earlier board the two leds can't be controlled seperately, should be fixed in rev. B and C boards. + +Signed-off-by: Koen Kooi <koen@openembedded.org> +--- + arch/arm/mach-omap2/board-omap3beagle.c | 28 ++++++++++++++++++++++++++++ + 1 files changed, 28 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c +index c992cc7..83891fc 100644 +--- a/arch/arm/mach-omap2/board-omap3beagle.c ++++ b/arch/arm/mach-omap2/board-omap3beagle.c +@@ -19,6 +19,7 @@ + #include <linux/err.h> + #include <linux/clk.h> + #include <linux/io.h> ++#include <linux/leds.h> + + #include <asm/hardware.h> + #include <asm/mach-types.h> +@@ -72,6 +73,32 @@ static struct omap_lcd_config omap3_beagle_lcd_config __initdata = { + .ctrl_name = "internal", + }; + ++struct gpio_led gpio_leds[] = { ++ { ++ .name = "beagleboard::led0", ++ .default_trigger = "none", ++ .gpio = 149, ++ }, ++ { ++ .name = "beagleboard::led1", ++ .default_trigger = "none", ++ .gpio = 150, ++ }, ++}; ++ ++static struct gpio_led_platform_data gpio_led_info = { ++ .leds = gpio_leds, ++ .num_leds = ARRAY_SIZE(gpio_leds), ++}; ++ ++static struct platform_device leds_gpio = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = &gpio_led_info, ++ }, ++}; ++ + static struct omap_board_config_kernel omap3_beagle_config[] __initdata = { + { OMAP_TAG_UART, &omap3_beagle_uart_config }, + { OMAP_TAG_MMC, &omap3beagle_mmc_config }, +@@ -83,6 +110,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = { + #ifdef CONFIG_RTC_DRV_TWL4030 + &omap3_beagle_twl4030rtc_device, + #endif ++ &leds_gpio, + }; + + static void __init omap3_beagle_init(void) +-- +1.5.4.3 + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0002-omap3-cpuidle.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0002-omap3-cpuidle.patch new file mode 100644 index 0000000..d35fd47 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/0002-omap3-cpuidle.patch @@ -0,0 +1,88 @@ +From: "Rajendra Nayak" <rnayak@ti.com> +To: <linux-omap@vger.kernel.org> +Subject: [PATCH 02/02] Kconfig changes +Date: Tue, 10 Jun 2008 12:39:02 +0530 + +Updates the CPUidle Kconfig + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> + +--- + arch/arm/Kconfig | 10 ++++++++++ + drivers/cpuidle/Kconfig | 28 ++++++++++++++++++++++------ + 2 files changed, 32 insertions(+), 6 deletions(-) + +Index: linux-omap-2.6/arch/arm/Kconfig +=================================================================== +--- linux-omap-2.6.orig/arch/arm/Kconfig 2008-06-10 11:43:10.790502713 +0530 ++++ linux-omap-2.6/arch/arm/Kconfig 2008-06-10 11:43:38.701604549 +0530 +@@ -954,6 +954,16 @@ config ATAGS_PROC + + endmenu + ++if (ARCH_OMAP) ++ ++menu "CPUIdle" ++ ++source "drivers/cpuidle/Kconfig" ++ ++endmenu ++ ++endif ++ + if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) + + menu "CPU Frequency scaling" +Index: linux-omap-2.6/drivers/cpuidle/Kconfig +=================================================================== +--- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-06-10 11:43:10.790502713 +0530 ++++ linux-omap-2.6/drivers/cpuidle/Kconfig 2008-06-10 12:06:36.139332151 +0530 +@@ -1,20 +1,36 @@ ++menu "CPU idle PM support" + + config CPU_IDLE + bool "CPU idle PM support" +- default ACPI ++ default n + help + CPU idle is a generic framework for supporting software-controlled + idle processor power management. It includes modular cross-platform + governors that can be swapped during runtime. + +- If you're using an ACPI-enabled platform, you should say Y here. ++ If you're using a mobile platform that supports CPU idle PM (e.g. ++ an ACPI-capable notebook), you should say Y here. ++ ++if CPU_IDLE ++ ++comment "Governors" + + config CPU_IDLE_GOV_LADDER +- bool ++ bool "ladder" + depends on CPU_IDLE +- default y ++ default n + + config CPU_IDLE_GOV_MENU +- bool ++ bool "menu" + depends on CPU_IDLE && NO_HZ +- default y ++ default n ++ help ++ This cpuidle governor evaluates all available states and chooses the ++ deepest state that meets all of the following constraints: BM activity, ++ expected time until next timer interrupt, and last break event time ++ delta. It is designed to minimize power consumption. Currently ++ dynticks is required. ++ ++endif # CPU_IDLE ++ ++endmenu + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/01-fix-timing-print.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/01-fix-timing-print.diff new file mode 100644 index 0000000..89fbe3a --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/01-fix-timing-print.diff @@ -0,0 +1,23 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sat, 5 Jul 2008 20:31:56 +0000 (+0100) +Subject: omapfb: fix video timings message +X-Git-Tag: beagle-5~3 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=2929b75035ebe8702ba2ff2c81b654c487701f64 + +omapfb: fix video timings message +--- + +diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c +index 418ed9f..1166a01 100644 +--- a/drivers/video/omap/omapfb_main.c ++++ b/drivers/video/omap/omapfb_main.c +@@ -1789,7 +1789,8 @@ static int omapfb_do_probe(struct platform_device *pdev, + vram, fbdev->mem_desc.region_cnt); + pr_info("omapfb: Pixclock %lu kHz hfreq %lu.%lu kHz " + "vfreq %lu.%lu Hz\n", +- phz / 1000, hhz / 10000, hhz % 10, vhz / 10, vhz % 10); ++ phz / 1000, hhz / 10000, hhz % 10000, ++ vhz / 10, vhz % 10); + + return 0; + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/01-gptimer_clear_isrs_on_init b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/01-gptimer_clear_isrs_on_init new file mode 100644 index 0000000..5123baf --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/01-gptimer_clear_isrs_on_init @@ -0,0 +1,25 @@ +clear + +From: Paul Walmsley <paul@pwsan.com> + + +--- + + arch/arm/plat-omap/dmtimer.c | 4 ++++ + 1 files changed, 4 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c +index f22506a..e38a11e 100644 +--- a/arch/arm/plat-omap/dmtimer.c ++++ b/arch/arm/plat-omap/dmtimer.c +@@ -703,6 +703,10 @@ int __init omap_dm_timer_init(void) + timer->fclk = clk_get(NULL, clk_name); + } + #endif ++ omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW | ++ OMAP_TIMER_INT_MATCH | ++ OMAP_TIMER_INT_CAPTURE); ++ + } + + return 0; diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/02-gptimer_use_match_for_tick b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/02-gptimer_use_match_for_tick new file mode 100644 index 0000000..6eb6c9b --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/02-gptimer_use_match_for_tick @@ -0,0 +1,97 @@ +OMAP2/3 system tick GPTIMER: use match interrupts rather than overflow interrupts + +From: Paul Walmsley <paul@pwsan.com> + +On some OMAP3 chips, GPTIMER1 will occasionally decline to interrupt +the MPU when a timer overflow event occurs. The timer stops running; +and TOCR is sometimes incremented; but the MPU apparently never receives +the interrupt. This patch was an experiment in using the GPTIMER +match interrupt to determine if it resolves the problem. +Unfortunately, it does not; the same problem occurs with match +interrupts; but this patch is preserved as the base for a +match+overflow interrupt workaround used in a following patch. +--- + + arch/arm/mach-omap2/timer-gp.c | 32 ++++++++++---------------------- + 1 files changed, 10 insertions(+), 22 deletions(-) + +diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c +index 557603f..51996ba 100644 +--- a/arch/arm/mach-omap2/timer-gp.c ++++ b/arch/arm/mach-omap2/timer-gp.c +@@ -36,6 +36,8 @@ + #include <asm/mach/time.h> + #include <asm/arch/dmtimer.h> + ++#define GPTIMER_MATCH_VAL 0xffff0000 ++ + static struct omap_dm_timer *gptimer; + static struct clock_event_device clockevent_gpt; + +@@ -44,7 +46,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) + struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id; + struct clock_event_device *evt = &clockevent_gpt; + +- omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW); ++ omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_MATCH); + + evt->event_handler(evt); + return IRQ_HANDLED; +@@ -59,7 +61,7 @@ static struct irqaction omap2_gp_timer_irq = { + static int omap2_gp_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) + { +- omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles); ++ omap_dm_timer_set_load_start(gptimer, 0, GPTIMER_MATCH_VAL - cycles); + + return 0; + } +@@ -67,29 +69,12 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles, + static void omap2_gp_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) + { +- u32 period; +- + omap_dm_timer_stop(gptimer); +- +- switch (mode) { +- case CLOCK_EVT_MODE_PERIODIC: +- period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; +- period -= 1; +- +- omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period); +- break; +- case CLOCK_EVT_MODE_ONESHOT: +- break; +- case CLOCK_EVT_MODE_UNUSED: +- case CLOCK_EVT_MODE_SHUTDOWN: +- case CLOCK_EVT_MODE_RESUME: +- break; +- } + } + + static struct clock_event_device clockevent_gpt = { + .name = "gp timer", +- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, ++ .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_next_event = omap2_gp_timer_set_next_event, + .set_mode = omap2_gp_timer_set_mode, +@@ -111,12 +96,15 @@ static void __init omap2_gp_clockevent_init(void) + + omap2_gp_timer_irq.dev_id = (void *)gptimer; + setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); +- omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); ++ omap_dm_timer_stop(gptimer); ++ /* omap_dm_timer_set_load(gptimer, 0, 0);*/ ++ omap_dm_timer_set_match(gptimer, 1, GPTIMER_MATCH_VAL); ++ omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_MATCH); + + clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC, + clockevent_gpt.shift); + clockevent_gpt.max_delta_ns = +- clockevent_delta2ns(0xffffffff, &clockevent_gpt); ++ clockevent_delta2ns(GPTIMER_MATCH_VAL, &clockevent_gpt); + clockevent_gpt.min_delta_ns = + clockevent_delta2ns(1, &clockevent_gpt); + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/02-set-clkseld11.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/02-set-clkseld11.diff new file mode 100644 index 0000000..c437f14 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/02-set-clkseld11.diff @@ -0,0 +1,22 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sat, 5 Jul 2008 20:32:38 +0000 (+0100) +Subject: omap: set CLKSEL_DSS1 to 2 +X-Git-Tag: beagle-5~2 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=d23f9c3c5c6243b626f7ec4c255469de2536e488 + +omap: set CLKSEL_DSS1 to 2 +--- + +diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c +index 8fdf8f3..04dedec 100644 +--- a/arch/arm/mach-omap2/clock34xx.c ++++ b/arch/arm/mach-omap2/clock34xx.c +@@ -596,6 +596,8 @@ int __init omap2_clk_init(void) + /* u32 clkrate; */ + u32 cpu_clkflg; + ++ __raw_writel(0x1002, io_p2v(0x48004e40)); ++ + /* REVISIT: Ultimately this will be used for multiboot */ + #if 0 + if (cpu_is_omap242x()) { diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/03-enable-overlay-opt.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/03-enable-overlay-opt.diff new file mode 100644 index 0000000..9fa749f --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/03-enable-overlay-opt.diff @@ -0,0 +1,27 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sun, 6 Jul 2008 13:15:36 +0000 (+0100) +Subject: omapfb: enable overlay optimisation when possible +X-Git-Tag: beagle-5~1 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=a63ac3abdf6781f863112321260fe7a5da757802 + +omapfb: enable overlay optimisation when possible +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 6aff476..3b36227 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -582,11 +582,13 @@ static int omap_dispc_enable_plane(int plane, int enable) + const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES, + DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES, + DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES }; ++ unsigned overlay_opt = plane & !!enable & !dispc.color_key.key_type; + if ((unsigned int)plane > dispc.mem_desc.region_cnt) + return -EINVAL; + + enable_lcd_clocks(1); + MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0); ++ MOD_REG_FLD(DISPC_CONTROL, 1<<12 | 1<<5, overlay_opt<<12 | 1<<5); + enable_lcd_clocks(0); + + return 0; diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/03-gptimer_match_plus_ovf b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/03-gptimer_match_plus_ovf new file mode 100644 index 0000000..3de6e05 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/03-gptimer_match_plus_ovf @@ -0,0 +1,94 @@ +OMAP2/3 system tick GPTIMER: use overflow interrupts to detect missing match interrupts + +From: Paul Walmsley <paul@pwsan.com> + +GPTIMER1 on some OMAP3 chips occasionally misses match conditions +between the timer counter and the target register value, and does not +interrupt to the MPU. This patch adds another line of defense by +setting the timer to generate an overflow interrupt 0.5 seconds after the +timer passes the original comparison value. + +If interrupts are masked for a long period of time, one would expect +both a match and an overflow interrupt to be logged. This is considered +a normal condition. However, if only an overflow interrupt is logged, +this is considered evidence of a hardware bug and the kernel will issue +a warning. + +This workaround is unlikely to be 100% effective, since GPTIMER1 has +also been observed to lose overflow interrupts occasionally. It is +hoped that the probability of losing both will be significantly lower +than the probability of losing either one. +--- + + arch/arm/mach-omap2/timer-gp.c | 36 ++++++++++++++++++++++++++++++++---- + 1 files changed, 32 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c +index 51996ba..ce5c2b4 100644 +--- a/arch/arm/mach-omap2/timer-gp.c ++++ b/arch/arm/mach-omap2/timer-gp.c +@@ -36,17 +36,43 @@ + #include <asm/mach/time.h> + #include <asm/arch/dmtimer.h> + +-#define GPTIMER_MATCH_VAL 0xffff0000 ++/* ++ * The number of timer ticks to delay will be subtracted from ++ * GPTIMER_MATCH_VAL before loading into the timer. So GPTIMER_MATCH_VAL ++ * constrains the longest delay that can be generated with the timer. ++ * Since the current code uses overflow interrupts as protection against ++ * missed comparison interrupts, this value should also be sufficiently ++ * large such that there is not an excessively long delay between ticks ++ * if the comparison interrupt fails to arrive. The 0xfffff800 value ++ * below results in a half-second delay in such a case when using ++ * the 32kHz timer as source. ++ */ ++#define GPTIMER_MATCH_VAL (0xffffffff - (32768/2)) + + static struct omap_dm_timer *gptimer; + static struct clock_event_device clockevent_gpt; + ++static u32 last_load; ++ + static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) + { + struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id; + struct clock_event_device *evt = &clockevent_gpt; +- +- omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_MATCH); ++ u32 v; ++ ++ v = omap_dm_timer_read_status(gpt); ++ if ((v & OMAP_TIMER_INT_OVERFLOW) && !(v & OMAP_TIMER_INT_MATCH)) { ++ /* ++ * Should never happen. Current belief is that this is ++ * due to a hardware bug in the GPTIMER block on some ++ * OMAP3 revisions. ++ */ ++ pr_err("*** GPTIMER missed match interrupt! last load: %08x\n", ++ last_load); ++ WARN_ON(1); ++ } ++ ++ omap_dm_timer_write_status(gpt, v); + + evt->event_handler(evt); + return IRQ_HANDLED; +@@ -61,6 +87,7 @@ static struct irqaction omap2_gp_timer_irq = { + static int omap2_gp_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) + { ++ last_load = GPTIMER_MATCH_VAL - cycles; + omap_dm_timer_set_load_start(gptimer, 0, GPTIMER_MATCH_VAL - cycles); + + return 0; +@@ -99,7 +126,8 @@ static void __init omap2_gp_clockevent_init(void) + omap_dm_timer_stop(gptimer); + /* omap_dm_timer_set_load(gptimer, 0, 0);*/ + omap_dm_timer_set_match(gptimer, 1, GPTIMER_MATCH_VAL); +- omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_MATCH); ++ omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_MATCH | ++ OMAP_TIMER_INT_OVERFLOW); + + clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC, + clockevent_gpt.shift); diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/04-gptimer_add_debug_to_sysrq_q b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/04-gptimer_add_debug_to_sysrq_q new file mode 100644 index 0000000..aa9f098 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/04-gptimer_add_debug_to_sysrq_q @@ -0,0 +1,110 @@ +Add extra debug for the q_d_w_o() when work fn is already active. + +From: Paul Walmsley <paul@pwsan.com> + + +--- + + arch/arm/mach-omap2/timer-gp.c | 3 ++- + arch/arm/plat-omap/dmtimer.c | 20 ++++++++++++++++++++ + include/asm-arm/arch-omap/dmtimer.h | 1 + + kernel/time/timer_list.c | 8 ++++++++ + 4 files changed, 31 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c +index ce5c2b4..e3ed368 100644 +--- a/arch/arm/mach-omap2/timer-gp.c ++++ b/arch/arm/mach-omap2/timer-gp.c +@@ -50,6 +50,7 @@ + #define GPTIMER_MATCH_VAL (0xffffffff - (32768/2)) + + static struct omap_dm_timer *gptimer; ++struct omap_dm_timer *gptimer_pub; + static struct clock_event_device clockevent_gpt; + + static u32 last_load; +@@ -111,7 +112,7 @@ static void __init omap2_gp_clockevent_init(void) + { + u32 tick_rate; + +- gptimer = omap_dm_timer_request_specific(1); ++ gptimer = gptimer_pub = omap_dm_timer_request_specific(1); + BUG_ON(gptimer == NULL); + + #if defined(CONFIG_OMAP_32K_TIMER) +diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c +index e38a11e..b10f8ac 100644 +--- a/arch/arm/plat-omap/dmtimer.c ++++ b/arch/arm/plat-omap/dmtimer.c +@@ -614,6 +614,26 @@ void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, + omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value); + } + ++void omap_dm_timer_dump_int_enable(struct omap_dm_timer *timer) ++{ ++ u32 l; ++ l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG); ++ pr_err("GPT TCRR: %08x\n", l); ++ l = omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG); ++ pr_err("GPT TMAT: %08x\n", l); ++ l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG); ++ pr_err("GPT TISR: %08x\n", l); ++ l = omap_dm_timer_read_reg(timer, OMAP_TIMER_INT_EN_REG); ++ pr_err("GPT TIER: %08x\n", l); ++ l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); ++ pr_err("GPT TCLR: %08x\n", l); ++ l = omap_dm_timer_read_reg(timer, OMAP_TIMER_TICK_INT_MASK_SET_REG); ++ pr_err("GPT TOCR: %08x\n", l); ++ l = omap_dm_timer_read_reg(timer, OMAP_TIMER_TICK_INT_MASK_COUNT_REG); ++ pr_err("GPT TOWR: %08x\n", l); ++} ++ ++ + unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) + { + unsigned int l; +diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h +index 02b29e8..a8123e9 100644 +--- a/include/asm-arm/arch-omap/dmtimer.h ++++ b/include/asm-arm/arch-omap/dmtimer.h +@@ -73,6 +73,7 @@ void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); + + void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); + ++void omap_dm_timer_dump_int_enable(struct omap_dm_timer *timer); + unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer); + void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); + unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer); +diff --git a/kernel/time/timer_list.c b/kernel/time/timer_list.c +index a40e20f..452eab7 100644 +--- a/kernel/time/timer_list.c ++++ b/kernel/time/timer_list.c +@@ -18,6 +18,8 @@ + #include <linux/kallsyms.h> + #include <linux/tick.h> + ++#include <asm/arch/dmtimer.h> ++ + #include <asm/uaccess.h> + + typedef void (*print_fn_t)(struct seq_file *m, unsigned int *classes); +@@ -239,6 +241,8 @@ static void timer_list_show_tickdevices(struct seq_file *m) + static void timer_list_show_tickdevices(struct seq_file *m) { } + #endif + ++extern struct omap_dm_timer *gptimer_pub; ++ + static int timer_list_show(struct seq_file *m, void *v) + { + u64 now = ktime_to_ns(ktime_get()); +@@ -254,6 +258,10 @@ static int timer_list_show(struct seq_file *m, void *v) + SEQ_printf(m, "\n"); + timer_list_show_tickdevices(m); + ++ SEQ_printf(m, "\n"); ++ ++ omap_dm_timer_dump_int_enable(gptimer_pub); ++ + return 0; + } + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/04-use-pcd.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/04-use-pcd.diff new file mode 100644 index 0000000..bdf8ab5 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/04-use-pcd.diff @@ -0,0 +1,28 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sun, 6 Jul 2008 13:22:54 +0000 (+0100) +Subject: omapfb: use PCD if set in panel config +X-Git-Tag: beagle-5 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=c8060d36ae156771f00a7a27cabf1b4435c378bd + +omapfb: use PCD if set in panel config +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 3b36227..4e1a8e3 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -798,7 +798,13 @@ static void set_lcd_timings(void) + l |= panel->acb & 0xff; + dispc_write_reg(DISPC_POL_FREQ, l); + +- calc_ck_div(is_tft, panel->pixel_clock * 1000, &lck_div, &pck_div); ++ if (panel->pcd) { ++ pck_div = panel->pcd; ++ lck_div = 1; ++ } else { ++ calc_ck_div(is_tft, panel->pixel_clock * 1000, ++ &lck_div, &pck_div); ++ } + + l = dispc_read_reg(DISPC_DIVISOR); + l &= ~(FLD_MASK(16, 8) | FLD_MASK(0, 8)); diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/05-fix-display-panning.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/05-fix-display-panning.diff new file mode 100644 index 0000000..d3c9fff --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/05-fix-display-panning.diff @@ -0,0 +1,45 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Mon, 7 Jul 2008 00:13:00 +0000 (+0100) +Subject: omapfb: fix display panning +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=9fec252c96b0e69bcef0afd9cb9dd72b7179c239 + +omapfb: fix display panning +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 4e1a8e3..c17371c 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -435,6 +435,8 @@ static inline int _setup_plane(int plane, int channel_out, + + dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1); + ++ MOD_REG_FLD(DISPC_CONTROL, 1<<5, 1<<5); ++ + return height * screen_width * bpp / 8; + } + +diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c +index 1166a01..3e4959e 100644 +--- a/drivers/video/omap/omapfb_main.c ++++ b/drivers/video/omap/omapfb_main.c +@@ -206,8 +206,8 @@ static int ctrl_change_mode(struct fb_info *fbi) + struct omapfb_device *fbdev = plane->fbdev; + struct fb_var_screeninfo *var = &fbi->var; + +- offset = var->yoffset * fbi->fix.line_length + +- var->xoffset * var->bits_per_pixel / 8; ++ offset = (var->yoffset * var->xres_virtual + var->xoffset) * ++ var->bits_per_pixel / 8; + + if (fbdev->ctrl->sync) + fbdev->ctrl->sync(); +@@ -423,6 +423,8 @@ static void set_fb_fix(struct fb_info *fbi) + } + fix->accel = FB_ACCEL_OMAP1610; + fix->line_length = var->xres_virtual * bpp / 8; ++ fix->xpanstep = 1; ++ fix->ypanstep = 1; + } + + static int set_color_mode(struct omapfb_plane_struct *plane, diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/06-ensure-fclk.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/06-ensure-fclk.diff new file mode 100644 index 0000000..79871a7 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/06-ensure-fclk.diff @@ -0,0 +1,31 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Mon, 7 Jul 2008 23:59:08 +0000 (+0100) +Subject: omapfb: ensure fck/lcd < 173MHz +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=0523ece1bad659c48c66aea364d83f7490e7e5ae + +omapfb: ensure fck/lcd < 173MHz +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index c17371c..85d6cad 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -738,14 +738,16 @@ static void setup_color_conv_coef(void) + MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range); + } + ++#define MAX_FCK_LCD 173000000 ++ + static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div) + { + unsigned long fck, lck; + +- *lck_div = 1; + pck = max(1, pck); + fck = clk_get_rate(dispc.dss1_fck); +- lck = fck; ++ *lck_div = (fck + MAX_FCK_LCD - 1) / MAX_FCK_LCD; ++ lck = fck / *lck_div; + *pck_div = (lck + pck - 1) / pck; + if (is_tft) + *pck_div = max(2, *pck_div); diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/07-set-burst-size.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/07-set-burst-size.diff new file mode 100644 index 0000000..99bd80e --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/07-set-burst-size.diff @@ -0,0 +1,21 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Tue, 8 Jul 2008 18:26:43 +0000 (+0100) +Subject: omapfb: set graphics burst size to 16x32 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=4f9e415dfcd5613a8de973f6c9878cab959c5869 + +omapfb: set graphics burst size to 16x32 +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 85d6cad..fd06ca2 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -409,7 +409,7 @@ static inline int _setup_plane(int plane, int channel_out, + l |= cconv_en << 9; + + l &= ~(0x03 << burst_shift); +- l |= DISPC_BURST_8x32 << burst_shift; ++ l |= DISPC_BURST_16x32 << burst_shift; + + l &= ~(1 << chout_shift); + l |= chout_val << chout_shift; diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/16bpp.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/16bpp.patch new file mode 100644 index 0000000..d2bff4b --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/16bpp.patch @@ -0,0 +1,137 @@ +diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig +index bdeb8fb..bf256f3 100644 +--- a/drivers/video/omap/Kconfig ++++ b/drivers/video/omap/Kconfig +@@ -7,6 +7,27 @@ config FB_OMAP + help + Frame buffer driver for OMAP based boards. + ++choice ++ depends on FB_OMAP && MACH_OMAP3_BEAGLE ++ prompt "Screen resolution" ++ default FB_OMAP_079M3R ++ help ++ Selected desired screen resolution ++ ++config FB_OMAP_031M3R ++ boolean "640 x 480 @ 60 Hz Reduced blanking" ++ ++config FB_OMAP_048M3R ++ boolean "800 x 600 @ 60 Hz Reduced blanking" ++ ++config FB_OMAP_079M3R ++ boolean "1024 x 768 @ 60 Hz Reduced blanking" ++ ++config FB_OMAP_092M9R ++ boolean "1280 x 720 @ 60 Hz Reduced blanking" ++ ++endchoice ++ + config FB_OMAP_LCDC_EXTERNAL + bool "External LCD controller support" + depends on FB_OMAP +diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c +index 69d4e06..5e098c2 100644 +--- a/drivers/video/omap/lcd_omap3beagle.c ++++ b/drivers/video/omap/lcd_omap3beagle.c +@@ -31,10 +31,6 @@ + + #define LCD_PANEL_ENABLE_GPIO 170 + +-#define LCD_XRES 1024 +-#define LCD_YRES 768 +-#define LCD_PIXCLOCK 64000 /* in kHz */ +- + static int omap3beagle_panel_init(struct lcd_panel *panel, + struct omapfb_device *fbdev) + { +@@ -65,19 +61,76 @@ static unsigned long omap3beagle_panel_get_caps(struct lcd_panel *panel) + struct lcd_panel omap3beagle_panel = { + .name = "omap3beagle", + .config = OMAP_LCDC_PANEL_TFT, +- +- .bpp = 24, ++ .bpp = 16, + .data_lines = 24, +- .x_res = LCD_XRES, +- .y_res = LCD_YRES, +- .hsw = 3, /* hsync_len (4) - 1 */ +- .hfp = 3, /* right_margin (4) - 1 */ +- .hbp = 39, /* left_margin (40) - 1 */ +- .vsw = 1, /* vsync_len (2) - 1 */ +- .vfp = 2, /* lower_margin */ +- .vbp = 7, /* upper_margin (8) - 1 */ +- +- .pixel_clock = LCD_PIXCLOCK, ++ ++#if defined CONFIG_FB_OMAP_031M3R ++ ++ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */ ++ .x_res = 640, ++ .y_res = 480, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 7, ++ .pixel_clock = 23500, ++ ++#elif defined CONFIG_FB_OMAP_048M3R ++ ++ /* 800 x 600 @ 60 Hz Reduced blanking VESA CVT 0.48M3-R */ ++ .x_res = 800, ++ .y_res = 600, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 11, ++ .pixel_clock = 35500, ++ ++#elif defined CONFIG_FB_OMAP_079M3R ++ ++ /* 1024 x 768 @ 60 Hz Reduced blanking VESA CVT 0.79M3-R */ ++ .x_res = 1024, ++ .y_res = 768, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 15, ++ .pixel_clock = 56000, ++ ++#elif defined CONFIG_FB_OMAP_092M9R ++ ++ /* 1280 x 720 @ 60 Hz Reduced blanking VESA CVT 0.92M9-R */ ++ .x_res = 1280, ++ .y_res = 720, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 5, ++ .vbp = 13, ++ .pixel_clock = 64000, ++ ++#else ++ ++ /* use 640 x 480 if no config option */ ++ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */ ++ .x_res = 640, ++ .y_res = 480, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 7, ++ .pixel_clock = 23500, ++ ++#endif + + .init = omap3beagle_panel_init, + .cleanup = omap3beagle_panel_cleanup, + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/400khz-i2c.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/400khz-i2c.diff new file mode 100644 index 0000000..f749dbc --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/400khz-i2c.diff @@ -0,0 +1,22 @@ +From: Steve Sakoman <steve@sakoman.com> +Date: Wed, 16 Jul 2008 19:38:43 +0000 (-0700) +Subject: omap3beagle: set data rate on i2c-1 to 400, since 2600 seems to be +X-Git-Url: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=commitdiff_plain;h=12d6504334a830774ff1d42cee4b7296ac9fb7d2 + +omap3beagle: set data rate on i2c-1 to 400, since 2600 seems to be +flakey +--- + +diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c +index fdce787..938ad73 100644 +--- a/arch/arm/mach-omap2/board-omap3beagle.c ++++ b/arch/arm/mach-omap2/board-omap3beagle.c +@@ -39,7 +39,7 @@ static struct omap_uart_config omap3_beagle_uart_config __initdata = { + + static int __init omap3_beagle_i2c_init(void) + { +- omap_register_i2c_bus(1, 2600, NULL, 0); ++ omap_register_i2c_bus(1, 400, NULL, 0); + omap_register_i2c_bus(2, 400, NULL, 0); + omap_register_i2c_bus(3, 400, NULL, 0); + return 0; diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/4bitmmc.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/4bitmmc.diff new file mode 100644 index 0000000..5cd120c --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/4bitmmc.diff @@ -0,0 +1,38 @@ +From: Purushotam Kumar <purushotam@ti.com> +Date: Fri, 18 Jul 2008 23:28:57 +0000 (-0700) +Subject: OMAP3:devices.c:Enabling 4-bit for SD card +X-Git-Url: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=commitdiff_plain;h=6c4d34031c80ca4b50ffe73a4ef7fe197a760a60 + +OMAP3:devices.c:Enabling 4-bit for SD card + +SD card was working in 1-bit mode.This patch will configure SD card in +4-bit mode and hence performance will increase. + +Signed-off-by: Purushotam Kumar <purushotam@ti.com> +Acked-by: Madhusudhan Chikkature Rajashekar <madhu.cr@ti.com> +--- + +diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c +index b83f9a6..d0cfceb 100644 +--- a/arch/arm/plat-omap/devices.c ++++ b/arch/arm/plat-omap/devices.c +@@ -296,13 +296,17 @@ static void __init omap_init_mmc(void) + mmc = &mmc_conf->mmc[0]; + + if (cpu_is_omap2430() || cpu_is_omap34xx()) { +- if (mmc->enabled) ++ if (mmc->enabled) { ++ mmc1_data.conf = *mmc; + (void) platform_device_register(&mmc_omap_device1); ++ } + + #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) + mmc = &mmc_conf->mmc[1]; +- if (mmc->enabled) ++ if (mmc->enabled) { ++ mmc2_data.conf = *mmc; + (void) platform_device_register(&mmc_omap_device2); ++ } + #endif + + return; diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-01.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-01.patch new file mode 100644 index 0000000..c361c33 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-01.patch @@ -0,0 +1,43 @@ +TWL4030: remove superfluous PWR interrupt status clear before masking + +From: Paul Walmsley <paul@pwsan.com> + +twl_irq_init() clears PWR interrupt status bits, then masks the interrupts +off, then clears the PWR interrupt status bits again. The first clear +seems unnecessary, so, remove it. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + drivers/i2c/chips/twl4030-core.c | 18 ------------------ + 1 files changed, 0 insertions(+), 18 deletions(-) + +diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c +index adc45d4..ff662bc 100644 +--- a/drivers/i2c/chips/twl4030-core.c ++++ b/drivers/i2c/chips/twl4030-core.c +@@ -719,24 +719,6 @@ static void twl_init_irq(void) + char *msg = "Unable to register interrupt subsystem"; + unsigned int irq_num; + +- /* +- * We end up with interrupts from other modules before +- * they get a chance to handle them... +- */ +- /* PWR_ISR1 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x00); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } +- +- /* PWR_ISR2 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x02); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } +- + /* PWR_IMR1 */ + res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x1); + if (res < 0) { diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-02.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-02.patch new file mode 100644 index 0000000..48a59b9 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-02.patch @@ -0,0 +1,71 @@ +TWL4030: clear TWL GPIO interrupt status registers + +From: Paul Walmsley <paul@pwsan.com> + +twl_init_irq() does not clear the TWL GPIO ISR registers, but the PIH +ISR thinks that it has. This causes any previously-latched GPIO interrupts +to be stuck on until twl4030-gpio.c initializes, often drowning the console in + + TWL4030 module irq 368 is disabled but can't be masked! + +messages. This seems to be a particular problem when booting on Beagle. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + drivers/i2c/chips/twl4030-core.c | 42 ++++++++++++++++++++++++++++++++++++++ + 1 files changed, 42 insertions(+), 0 deletions(-) + +diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c +index ff662bc..dfc3805 100644 +--- a/drivers/i2c/chips/twl4030-core.c ++++ b/drivers/i2c/chips/twl4030-core.c +@@ -857,6 +857,48 @@ static void twl_init_irq(void) + return; + } + ++ /* GPIO_ISR1A */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x19); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ ++ /* GPIO_ISR2A */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1a); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ ++ /* GPIO_ISR3A */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1b); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ ++ /* GPIO_ISR1B */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1f); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ ++ /* GPIO_ISR2B */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x20); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ ++ /* GPIO_ISR3B */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x21); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ + /* install an irq handler for each of the PIH modules */ + for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) { + set_irq_chip(i, &twl4030_irq_chip); diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-03.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-03.patch new file mode 100644 index 0000000..fe1bea5 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-03.patch @@ -0,0 +1,82 @@ +TWL4030: use correct register addresses for BCI IMR registers + +From: Paul Walmsley <paul@pwsan.com> + +The existing code to mask and clear BCI interrupts in twl_init_irq() is +wrong. It uses the wrong register offsets, it does not mask all of the +BCI IMR registers, and it does not clear all of the BCI ISR registers. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + drivers/i2c/chips/twl4030-core.c | 40 ++++++++++++++++++++++++++++++++------ + 1 files changed, 34 insertions(+), 6 deletions(-) + +diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c +index dfc3805..bb0732c 100644 +--- a/drivers/i2c/chips/twl4030-core.c ++++ b/drivers/i2c/chips/twl4030-core.c +@@ -750,29 +750,57 @@ static void twl_init_irq(void) + /* POWER HACK (END) */ + /* Slave address 0x4A */ + +- /* BCIIMR1_1 */ ++ /* BCIIMR1A */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x2); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ ++ /* BCIIMR2A */ + res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x3); + if (res < 0) { + pr_err("%s[%d][%d]\n", msg, res, __LINE__); + return; + } + +- /* BCIIMR1_2 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x4); ++ /* BCIIMR1B */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x6); + if (res < 0) { + pr_err("%s[%d][%d]\n", msg, res, __LINE__); + return; + } + +- /* BCIIMR2_1 */ ++ /* BCIIMR2B */ + res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x7); + if (res < 0) { + pr_err("%s[%d][%d]\n", msg, res, __LINE__); + return; + } + +- /* BCIIMR2_2 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x8); ++ /* BCIISR1A */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x0); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ ++ /* BCIISR2A */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x1); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ ++ /* BCIISR1B */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x4); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ ++ /* BCIISR2B */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x5); + if (res < 0) { + pr_err("%s[%d][%d]\n", msg, res, __LINE__); + return; diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-04.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-04.patch new file mode 100644 index 0000000..fb65ac9 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-04.patch @@ -0,0 +1,38 @@ +TWL4030: clear MADC interrupt status registers upon init + +From: Paul Walmsley <paul@pwsan.com> + +twl_init_irq() does not clear MADC interrupt status registers upon init - +fix. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + drivers/i2c/chips/twl4030-core.c | 14 ++++++++++++++ + 1 files changed, 14 insertions(+), 0 deletions(-) + +diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c +index bb0732c..9d93524 100644 +--- a/drivers/i2c/chips/twl4030-core.c ++++ b/drivers/i2c/chips/twl4030-core.c +@@ -821,6 +821,20 @@ static void twl_init_irq(void) + return; + } + ++ /* MADC_ISR1 */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x61); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ ++ /* MADC_ISR2 */ ++ res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x63); ++ if (res < 0) { ++ pr_err("%s[%d][%d]\n", msg, res, __LINE__); ++ return; ++ } ++ + /* key Pad */ + /* KEYPAD - IMR1 */ + res = twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xFF, (0x12)); diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-05.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-05.patch new file mode 100644 index 0000000..02a72ed --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-05.patch @@ -0,0 +1,303 @@ +TWL4030: use *_SIH_CTRL.COR bit to determine whether to read or write ISR to clear + +From: Paul Walmsley <paul@pwsan.com> + +TWL4030 interrupt status register bits can be cleared in one of two ways: +either by reading from the register, or by writing a 1 to the +appropriate bit(s) in the register. This behavior can be altered at any +time by the <twlmodule>_SIH_CTRL.COR register bit ("clear-on-read"). + +The TWL4030 TRM is deeply confused as to whether COR=1 means that the +registers are cleared on reads, or cleared on writes. Peter De +Schrijver <peter.de-schrijver> confirms that COR=1 means that the registers +are cleared on read. + +So, for each TWL4030 SIH, check the value of the *_SIH_CTRL.COR bit, and if +it is 1, use reads to clear the ISRs; if it is 0, use writes. + +Also, use WARN_ON() to warn if the read/write failed, and don't skip +the rest of the initialization on failure either. + +Thanks to Peter for his help with this patch. + + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + drivers/i2c/chips/twl4030-core.c | 183 ++++++++++++++++++++++---------------- + 1 files changed, 106 insertions(+), 77 deletions(-) + +diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c +index 9d93524..eae0634 100644 +--- a/drivers/i2c/chips/twl4030-core.c ++++ b/drivers/i2c/chips/twl4030-core.c +@@ -133,6 +133,16 @@ + /* on I2C-1 for 2430SDP */ + #define CONFIG_I2C_TWL4030_ID 1 + ++/* SIH_CTRL registers */ ++#define TWL4030_INT_PWR_SIH_CTRL 0x07 ++#define TWL4030_INTERRUPTS_BCISIHCTRL 0x0d ++#define TWL4030_MADC_MADC_SIH_CTRL 0x67 ++#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17 ++#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2d ++ ++#define TWL4030_SIH_CTRL_COR_MASK (1 << 2) ++ ++ + /* Helper functions */ + static int + twl4030_detect_client(struct i2c_adapter *adapter, unsigned char sid); +@@ -712,13 +722,61 @@ static int power_companion_init(void) + return e; + } + ++/** ++ * twl4030_i2c_clear_isr - clear TWL4030 SIH ISR regs via read + write ++ * @mod_no: TWL4030 module number ++ * @reg: register index to clear ++ * @cor: value of the <module>_SIH_CTRL.COR bit (1 or 0) ++ * ++ * Either reads (cor == 1) or writes (cor == 0) to a TWL4030 interrupt ++ * status register to ensure that any prior interrupts are cleared. ++ * Returns the status from the I2C read operation. ++ */ ++static int twl4030_i2c_clear_isr(u8 mod_no, u8 reg, u8 cor) ++{ ++ u8 tmp; ++ ++ return (cor) ? twl4030_i2c_read_u8(mod_no, &tmp, reg) : ++ twl4030_i2c_write_u8(mod_no, 0xff, reg); ++} ++ ++/** ++ * twl4030_read_cor_bit - are TWL module ISRs cleared by reads or writes? ++ * @mod_no: TWL4030 module number ++ * @reg: register index to clear ++ * ++ * Returns 1 if the TWL4030 SIH interrupt status registers (ISRs) for ++ * the specified TWL module are cleared by reads, or 0 if cleared by ++ * writes. ++ */ ++static int twl4030_read_cor_bit(u8 mod_no, u8 reg) ++{ ++ u8 tmp = 0; ++ ++ WARN_ON(twl4030_i2c_read_u8(mod_no, &tmp, reg) < 0); ++ ++ tmp &= TWL4030_SIH_CTRL_COR_MASK; ++ tmp >>= __ffs(TWL4030_SIH_CTRL_COR_MASK); ++ ++ return tmp; ++} ++ + static void twl_init_irq(void) + { + int i = 0; + int res = 0; ++ int cor; + char *msg = "Unable to register interrupt subsystem"; + unsigned int irq_num; + ++ /* ++ * For each TWL4030 module with ISR/IMR registers, mask all ++ * interrupts and then clear any existing interrupt status bits, ++ * since we initially do not have any TWL4030 module interrupt ++ * handlers present. ++ */ ++ ++ + /* PWR_IMR1 */ + res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x1); + if (res < 0) { +@@ -734,20 +792,18 @@ static void twl_init_irq(void) + } + + /* Clear off any other pending interrupts on power */ ++ ++ /* Are PWR interrupt status bits cleared by reads or writes? */ ++ cor = twl4030_read_cor_bit(TWL4030_MODULE_INT, ++ TWL4030_INT_PWR_SIH_CTRL); ++ WARN_ON(cor < 0); ++ + /* PWR_ISR1 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x00); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x00, cor) < 0); + + /* PWR_ISR2 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x02); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } +- /* POWER HACK (END) */ ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x02, cor) < 0); ++ + /* Slave address 0x4A */ + + /* BCIIMR1A */ +@@ -778,33 +834,22 @@ static void twl_init_irq(void) + return; + } + ++ /* Are BCI interrupt status bits cleared by reads or writes? */ ++ cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS, ++ TWL4030_INTERRUPTS_BCISIHCTRL); ++ WARN_ON(cor < 0); ++ + /* BCIISR1A */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x0); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x0, cor) < 0); + + /* BCIISR2A */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x1); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x1, cor) < 0); + + /* BCIISR1B */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x4); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x4, cor) < 0); + + /* BCIISR2B */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x5); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x5, cor) < 0); + + /* MAD C */ + /* MADC_IMR1 */ +@@ -821,19 +866,16 @@ static void twl_init_irq(void) + return; + } + ++ /* Are MADC interrupt status bits cleared by reads or writes? */ ++ cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC, ++ TWL4030_MADC_MADC_SIH_CTRL); ++ WARN_ON(cor < 0); ++ + /* MADC_ISR1 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x61); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x61, cor) < 0); + + /* MADC_ISR2 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x63); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x63, cor) < 0); + + /* key Pad */ + /* KEYPAD - IMR1 */ +@@ -842,12 +884,15 @@ static void twl_init_irq(void) + pr_err("%s[%d][%d]\n", msg, res, __LINE__); + return; + } +- { +- u8 clear; +- /* Clear ISR */ +- twl4030_i2c_read_u8(TWL4030_MODULE_KEYPAD, &clear, 0x11); +- twl4030_i2c_read_u8(TWL4030_MODULE_KEYPAD, &clear, 0x11); +- } ++ ++ /* Are keypad interrupt status bits cleared by reads or writes? */ ++ cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD, ++ TWL4030_KEYPAD_KEYP_SIH_CTRL); ++ WARN_ON(cor < 0); ++ ++ /* KEYPAD - ISR1 */ ++ /* XXX does this still need to be done twice for some reason? */ ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x11, cor) < 0); + + /* KEYPAD - IMR2 */ + res = twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xFF, (0x14)); +@@ -856,6 +901,9 @@ static void twl_init_irq(void) + return; + } + ++ /* KEYPAD - ISR2 */ ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x13, cor) < 0); ++ + /* Slave address 0x49 */ + /* GPIO_IMR1A */ + res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x1C)); +@@ -899,47 +947,28 @@ static void twl_init_irq(void) + return; + } + ++ /* Are GPIO interrupt status bits cleared by reads or writes? */ ++ cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO, ++ TWL4030_GPIO_GPIO_SIH_CTRL); ++ WARN_ON(cor < 0); ++ + /* GPIO_ISR1A */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x19); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x19, cor) < 0); + + /* GPIO_ISR2A */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1a); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1a, cor) < 0); + + /* GPIO_ISR3A */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1b); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1b, cor) < 0); + + /* GPIO_ISR1B */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1f); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1f, cor) < 0); + + /* GPIO_ISR2B */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x20); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x20, cor) < 0); + + /* GPIO_ISR3B */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x21); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x21, cor) < 0); + + /* install an irq handler for each of the PIH modules */ + for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) { diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-06.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-06.patch new file mode 100644 index 0000000..67b837c --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-06.patch @@ -0,0 +1,179 @@ +TWL4030: change init-time IMR mask code to WARN if error + +From: Paul Walmsley <paul@pwsan.com> + +twl_init_irq() prints error messages and returns if any interrupt mask +register writes fail. Change this to generate a warning traceback and +to continue execution rather than skipping TWL init. (These mask +writes should not fail at all unless either the I2C bus or the TWL4030 +is somehow wedged.) + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + drivers/i2c/chips/twl4030-core.c | 100 +++++++------------------------------- + 1 files changed, 18 insertions(+), 82 deletions(-) + +diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c +index eae0634..99cc143 100644 +--- a/drivers/i2c/chips/twl4030-core.c ++++ b/drivers/i2c/chips/twl4030-core.c +@@ -778,18 +778,10 @@ static void twl_init_irq(void) + + + /* PWR_IMR1 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x1); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x1) < 0); + + /* PWR_IMR2 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x3); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x3) < 0); + + /* Clear off any other pending interrupts on power */ + +@@ -807,32 +799,16 @@ static void twl_init_irq(void) + /* Slave address 0x4A */ + + /* BCIIMR1A */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x2); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x2) < 0); + +- /* BCIIMR2A */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x3); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ /* BCIIMR2A */ ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x3) < 0); + +- /* BCIIMR1B */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x6); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ /* BCIIMR2A */ ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x6) < 0); + + /* BCIIMR2B */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x7); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x7) < 0); + + /* Are BCI interrupt status bits cleared by reads or writes? */ + cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS, +@@ -853,18 +829,10 @@ static void twl_init_irq(void) + + /* MAD C */ + /* MADC_IMR1 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x62); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x62) < 0); + + /* MADC_IMR2 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x64); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x64) < 0); + + /* Are MADC interrupt status bits cleared by reads or writes? */ + cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC, +@@ -879,11 +847,7 @@ static void twl_init_irq(void) + + /* key Pad */ + /* KEYPAD - IMR1 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xFF, (0x12)); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x12) < 0); + + /* Are keypad interrupt status bits cleared by reads or writes? */ + cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD, +@@ -895,57 +859,29 @@ static void twl_init_irq(void) + WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x11, cor) < 0); + + /* KEYPAD - IMR2 */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xFF, (0x14)); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x14) < 0); + + /* KEYPAD - ISR2 */ + WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x13, cor) < 0); + + /* Slave address 0x49 */ + /* GPIO_IMR1A */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x1C)); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1c) < 0); + + /* GPIO_IMR2A */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x1D)); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1d) < 0); + + /* GPIO_IMR3A */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x1E)); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1e) < 0); + + /* GPIO_IMR1B */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x22)); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x22) < 0); + + /* GPIO_IMR2B */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x23)); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x23) < 0); + + /* GPIO_IMR3B */ +- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x24)); +- if (res < 0) { +- pr_err("%s[%d][%d]\n", msg, res, __LINE__); +- return; +- } ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x24) < 0); + + /* Are GPIO interrupt status bits cleared by reads or writes? */ + cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO, diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-07.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-07.patch new file mode 100644 index 0000000..8e4c4d6 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-07.patch @@ -0,0 +1,274 @@ +TWL4030: move TWL module register defs into separate include files + +From: Paul Walmsley <paul@pwsan.com> + +twl_init_irq() uses "magic numbers" to access TWL module IMR and ISR +registers. Symbolic constants are definitely preferred. + +Rather than duplicating already existing symbolic constants in +twl4030-gpio.c and twl4030-pwrirq.c, move the existing constants out +into include files. This patch should not change kernel behavior. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + drivers/i2c/chips/twl4030-gpio.c | 48 ----------------------- + drivers/i2c/chips/twl4030-pwrirq.c | 15 +++---- + include/linux/i2c/twl4030-gpio.h | 76 ++++++++++++++++++++++++++++++++++++ + include/linux/i2c/twl4030-pwrirq.h | 37 ++++++++++++++++++ + 4 files changed, 121 insertions(+), 55 deletions(-) + create mode 100644 include/linux/i2c/twl4030-gpio.h + create mode 100644 include/linux/i2c/twl4030-pwrirq.h + +diff --git a/drivers/i2c/chips/twl4030-gpio.c b/drivers/i2c/chips/twl4030-gpio.c +index f16a48b..9d17f45 100644 +--- a/drivers/i2c/chips/twl4030-gpio.c ++++ b/drivers/i2c/chips/twl4030-gpio.c +@@ -38,6 +38,7 @@ + + #include <linux/i2c.h> + #include <linux/i2c/twl4030.h> ++#include <linux/i2c/twl4030-gpio.h> + #include <linux/slab.h> + + #include <asm/arch/irqs.h> +@@ -47,53 +48,6 @@ + + #include <linux/device.h> + +-/* +- * GPIO Block Register definitions +- */ +- +-#define REG_GPIODATAIN1 0x0 +-#define REG_GPIODATAIN2 0x1 +-#define REG_GPIODATAIN3 0x2 +-#define REG_GPIODATADIR1 0x3 +-#define REG_GPIODATADIR2 0x4 +-#define REG_GPIODATADIR3 0x5 +-#define REG_GPIODATAOUT1 0x6 +-#define REG_GPIODATAOUT2 0x7 +-#define REG_GPIODATAOUT3 0x8 +-#define REG_CLEARGPIODATAOUT1 0x9 +-#define REG_CLEARGPIODATAOUT2 0xA +-#define REG_CLEARGPIODATAOUT3 0xB +-#define REG_SETGPIODATAOUT1 0xC +-#define REG_SETGPIODATAOUT2 0xD +-#define REG_SETGPIODATAOUT3 0xE +-#define REG_GPIO_DEBEN1 0xF +-#define REG_GPIO_DEBEN2 0x10 +-#define REG_GPIO_DEBEN3 0x11 +-#define REG_GPIO_CTRL 0x12 +-#define REG_GPIOPUPDCTR1 0x13 +-#define REG_GPIOPUPDCTR2 0x14 +-#define REG_GPIOPUPDCTR3 0x15 +-#define REG_GPIOPUPDCTR4 0x16 +-#define REG_GPIOPUPDCTR5 0x17 +-#define REG_GPIO_ISR1A 0x19 +-#define REG_GPIO_ISR2A 0x1A +-#define REG_GPIO_ISR3A 0x1B +-#define REG_GPIO_IMR1A 0x1C +-#define REG_GPIO_IMR2A 0x1D +-#define REG_GPIO_IMR3A 0x1E +-#define REG_GPIO_ISR1B 0x1F +-#define REG_GPIO_ISR2B 0x20 +-#define REG_GPIO_ISR3B 0x21 +-#define REG_GPIO_IMR1B 0x22 +-#define REG_GPIO_IMR2B 0x23 +-#define REG_GPIO_IMR3B 0x24 +-#define REG_GPIO_EDR1 0x28 +-#define REG_GPIO_EDR2 0x29 +-#define REG_GPIO_EDR3 0x2A +-#define REG_GPIO_EDR4 0x2B +-#define REG_GPIO_EDR5 0x2C +-#define REG_GPIO_SIH_CTRL 0x2D +- + /* BitField Definitions */ + + /* Data banks : 3 banks for 8 gpios each */ +diff --git a/drivers/i2c/chips/twl4030-pwrirq.c b/drivers/i2c/chips/twl4030-pwrirq.c +index a4d2e92..1afdb65 100644 +--- a/drivers/i2c/chips/twl4030-pwrirq.c ++++ b/drivers/i2c/chips/twl4030-pwrirq.c +@@ -27,10 +27,8 @@ + #include <linux/random.h> + #include <linux/kthread.h> + #include <linux/i2c/twl4030.h> ++#include <linux/i2c/twl4030-pwrirq.h> + +-#define PWR_ISR1 0 +-#define PWR_IMR1 1 +-#define PWR_SIH_CTRL 7 + #define PWR_SIH_CTRL_COR (1<<2) + + static u8 twl4030_pwrirq_mask; +@@ -93,7 +91,8 @@ static void do_twl4030_pwrmodule_irq(unsigned int irq, irq_desc_t *desc) + twl4030_pwrirq_mask |= 1 << (irq - TWL4030_PWR_IRQ_BASE); + local_irq_enable(); + twl4030_i2c_write_u8(TWL4030_MODULE_INT, +- twl4030_pwrirq_mask, PWR_IMR1); ++ twl4030_pwrirq_mask, ++ TWL4030_INT_PWR_IMR1); + } + } + } +@@ -115,7 +114,7 @@ static void do_twl4030_pwrirq(unsigned int irq, irq_desc_t *desc) + + local_irq_enable(); + ret = twl4030_i2c_read_u8(TWL4030_MODULE_INT, &pwr_isr, +- PWR_ISR1); ++ TWL4030_INT_PWR_ISR1); + if (ret) { + printk(KERN_WARNING + "I2C error %d while reading TWL4030" +@@ -151,7 +150,7 @@ static int twl4030_pwrirq_thread(void *data) + twl4030_pwrirq_mask &= ~local_unmask; + + twl4030_i2c_write_u8(TWL4030_MODULE_INT, twl4030_pwrirq_mask, +- PWR_IMR1); ++ TWL4030_INT_PWR_IMR1); + + local_irq_disable(); + if (!twl4030_pwrirq_pending_unmask) +@@ -172,14 +171,14 @@ static int __init twl4030_pwrirq_init(void) + twl4030_pwrirq_pending_unmask = 0; + + err = twl4030_i2c_write_u8(TWL4030_MODULE_INT, twl4030_pwrirq_mask, +- PWR_IMR1); ++ TWL4030_INT_PWR_IMR1); + if (err) + return err; + + /* Enable clear on read */ + + err = twl4030_i2c_write_u8(TWL4030_MODULE_INT, PWR_SIH_CTRL_COR, +- PWR_SIH_CTRL); ++ TWL4030_INT_PWR_SIH_CTRL); + if (err) + return err; + +diff --git a/include/linux/i2c/twl4030-gpio.h b/include/linux/i2c/twl4030-gpio.h +new file mode 100644 +index 0000000..7cbf610 +--- /dev/null ++++ b/include/linux/i2c/twl4030-gpio.h +@@ -0,0 +1,76 @@ ++/* ++ * twl4030-gpio.h - header for TWL4030 GPIO module ++ * ++ * Copyright (C) 2005-2006, 2008 Texas Instruments, Inc. ++ * Copyright (C) 2008 Nokia Corporation ++ * ++ * Based on tlv320aic23.c: ++ * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __TWL4030_GPIO_H_ ++#define __TWL4030_GPIO_H_ ++ ++/* ++ * GPIO Block Register definitions ++ */ ++ ++#define REG_GPIODATAIN1 0x0 ++#define REG_GPIODATAIN2 0x1 ++#define REG_GPIODATAIN3 0x2 ++#define REG_GPIODATADIR1 0x3 ++#define REG_GPIODATADIR2 0x4 ++#define REG_GPIODATADIR3 0x5 ++#define REG_GPIODATAOUT1 0x6 ++#define REG_GPIODATAOUT2 0x7 ++#define REG_GPIODATAOUT3 0x8 ++#define REG_CLEARGPIODATAOUT1 0x9 ++#define REG_CLEARGPIODATAOUT2 0xA ++#define REG_CLEARGPIODATAOUT3 0xB ++#define REG_SETGPIODATAOUT1 0xC ++#define REG_SETGPIODATAOUT2 0xD ++#define REG_SETGPIODATAOUT3 0xE ++#define REG_GPIO_DEBEN1 0xF ++#define REG_GPIO_DEBEN2 0x10 ++#define REG_GPIO_DEBEN3 0x11 ++#define REG_GPIO_CTRL 0x12 ++#define REG_GPIOPUPDCTR1 0x13 ++#define REG_GPIOPUPDCTR2 0x14 ++#define REG_GPIOPUPDCTR3 0x15 ++#define REG_GPIOPUPDCTR4 0x16 ++#define REG_GPIOPUPDCTR5 0x17 ++#define REG_GPIO_ISR1A 0x19 ++#define REG_GPIO_ISR2A 0x1A ++#define REG_GPIO_ISR3A 0x1B ++#define REG_GPIO_IMR1A 0x1C ++#define REG_GPIO_IMR2A 0x1D ++#define REG_GPIO_IMR3A 0x1E ++#define REG_GPIO_ISR1B 0x1F ++#define REG_GPIO_ISR2B 0x20 ++#define REG_GPIO_ISR3B 0x21 ++#define REG_GPIO_IMR1B 0x22 ++#define REG_GPIO_IMR2B 0x23 ++#define REG_GPIO_IMR3B 0x24 ++#define REG_GPIO_EDR1 0x28 ++#define REG_GPIO_EDR2 0x29 ++#define REG_GPIO_EDR3 0x2A ++#define REG_GPIO_EDR4 0x2B ++#define REG_GPIO_EDR5 0x2C ++#define REG_GPIO_SIH_CTRL 0x2D ++ ++#endif /* End of __TWL4030_GPIO_H */ +diff --git a/include/linux/i2c/twl4030-pwrirq.h b/include/linux/i2c/twl4030-pwrirq.h +new file mode 100644 +index 0000000..7a13368 +--- /dev/null ++++ b/include/linux/i2c/twl4030-pwrirq.h +@@ -0,0 +1,37 @@ ++/* ++ * twl4030-gpio.h - header for TWL4030 GPIO module ++ * ++ * Copyright (C) 2008 Texas Instruments, Inc. ++ * Copyright (C) 2008 Nokia Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __TWL4030_PWRIRQ_H_ ++#define __TWL4030_PWRIRQ_H_ ++ ++/* ++ * INT Module Register definitions ++ * (not all registers are defined below) ++ */ ++ ++#define TWL4030_INT_PWR_ISR1 0x0 ++#define TWL4030_INT_PWR_IMR1 0x1 ++#define TWL4030_INT_PWR_ISR2 0x2 ++#define TWL4030_INT_PWR_IMR2 0x3 ++#define TWL4030_INT_PWR_SIH_CTRL 0x7 ++ ++#endif /* End of __TWL4030_PWRIRQ_H */ diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-08.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-08.patch new file mode 100644 index 0000000..9af25a7 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-08.patch @@ -0,0 +1,278 @@ +TWL4030: use symbolic ISR/IMR register names during twl_init_irq() + +From: Paul Walmsley <paul@pwsan.com> + +twl_init_irq() uses a bunch of magic numbers as register indices; this +has already led to several errors, fixed earlier in this patch series. +Now use descriptive macros instead of magic numbers. This patch should +not change kernel behavior. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + drivers/i2c/chips/twl4030-core.c | 188 +++++++++++++++++++------------------- + 1 files changed, 96 insertions(+), 92 deletions(-) + +diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c +index 99cc143..38c227a 100644 +--- a/drivers/i2c/chips/twl4030-core.c ++++ b/drivers/i2c/chips/twl4030-core.c +@@ -40,6 +40,9 @@ + + #include <linux/i2c.h> + #include <linux/i2c/twl4030.h> ++#include <linux/i2c/twl4030-gpio.h> ++#include <linux/i2c/twl4030-madc.h> ++#include <linux/i2c/twl4030-pwrirq.h> + #include <linux/slab.h> + #include <linux/clk.h> + #include <linux/device.h> +@@ -114,6 +117,23 @@ + #define TWL4030_BASEADD_RTC 0x001C + #define TWL4030_BASEADD_SECURED_REG 0x0000 + ++/* TWL4030 BCI registers */ ++#define TWL4030_INTERRUPTS_BCIIMR1A 0x2 ++#define TWL4030_INTERRUPTS_BCIIMR2A 0x3 ++#define TWL4030_INTERRUPTS_BCIIMR1B 0x6 ++#define TWL4030_INTERRUPTS_BCIIMR2B 0x7 ++#define TWL4030_INTERRUPTS_BCIISR1A 0x0 ++#define TWL4030_INTERRUPTS_BCIISR2A 0x1 ++#define TWL4030_INTERRUPTS_BCIISR1B 0x4 ++#define TWL4030_INTERRUPTS_BCIISR2B 0x5 ++ ++/* TWL4030 keypad registers */ ++#define TWL4030_KEYPAD_KEYP_IMR1 0x12 ++#define TWL4030_KEYPAD_KEYP_IMR2 0x14 ++#define TWL4030_KEYPAD_KEYP_ISR1 0x11 ++#define TWL4030_KEYPAD_KEYP_ISR2 0x13 ++ ++ + /* Triton Core internal information (END) */ + + /* Few power values */ +@@ -133,12 +153,10 @@ + /* on I2C-1 for 2430SDP */ + #define CONFIG_I2C_TWL4030_ID 1 + +-/* SIH_CTRL registers */ +-#define TWL4030_INT_PWR_SIH_CTRL 0x07 ++/* SIH_CTRL registers that aren't defined elsewhere */ + #define TWL4030_INTERRUPTS_BCISIHCTRL 0x0d + #define TWL4030_MADC_MADC_SIH_CTRL 0x67 + #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17 +-#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2d + + #define TWL4030_SIH_CTRL_COR_MASK (1 << 2) + +@@ -776,135 +794,121 @@ static void twl_init_irq(void) + * handlers present. + */ + +- +- /* PWR_IMR1 */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x1) < 0); +- +- /* PWR_IMR2 */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x3) < 0); +- +- /* Clear off any other pending interrupts on power */ ++ /* Mask INT (PWR) interrupts at TWL4030 */ ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, ++ TWL4030_INT_PWR_IMR1) < 0); ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, ++ TWL4030_INT_PWR_IMR2) < 0); + + /* Are PWR interrupt status bits cleared by reads or writes? */ + cor = twl4030_read_cor_bit(TWL4030_MODULE_INT, + TWL4030_INT_PWR_SIH_CTRL); + WARN_ON(cor < 0); + +- /* PWR_ISR1 */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x00, cor) < 0); +- +- /* PWR_ISR2 */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x02, cor) < 0); ++ /* Clear TWL4030 INT (PWR) ISRs */ ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, ++ TWL4030_INT_PWR_ISR1, cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, ++ TWL4030_INT_PWR_ISR2, cor) < 0); + + /* Slave address 0x4A */ + +- /* BCIIMR1A */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x2) < 0); +- +- /* BCIIMR2A */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x3) < 0); +- +- /* BCIIMR2A */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x6) < 0); +- +- /* BCIIMR2B */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x7) < 0); ++ /* Mask BCI interrupts at TWL4030 */ ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, ++ TWL4030_INTERRUPTS_BCIIMR1A) < 0); ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, ++ TWL4030_INTERRUPTS_BCIIMR2A) < 0); ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, ++ TWL4030_INTERRUPTS_BCIIMR1B) < 0); ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, ++ TWL4030_INTERRUPTS_BCIIMR2B) < 0); + + /* Are BCI interrupt status bits cleared by reads or writes? */ + cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS, + TWL4030_INTERRUPTS_BCISIHCTRL); + WARN_ON(cor < 0); + +- /* BCIISR1A */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x0, cor) < 0); +- +- /* BCIISR2A */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x1, cor) < 0); +- +- /* BCIISR1B */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x4, cor) < 0); +- +- /* BCIISR2B */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x5, cor) < 0); ++ /* Clear TWL4030 BCI ISRs */ ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, ++ TWL4030_INTERRUPTS_BCIISR1A, cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, ++ TWL4030_INTERRUPTS_BCIISR2A, cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, ++ TWL4030_INTERRUPTS_BCIISR1B, cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, ++ TWL4030_INTERRUPTS_BCIISR2B, cor) < 0); + + /* MAD C */ +- /* MADC_IMR1 */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x62) < 0); +- +- /* MADC_IMR2 */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x64) < 0); ++ /* Mask MADC interrupts at TWL4030 */ ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, ++ TWL4030_MADC_IMR1) < 0); ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, ++ TWL4030_MADC_IMR2) < 0); + + /* Are MADC interrupt status bits cleared by reads or writes? */ + cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC, + TWL4030_MADC_MADC_SIH_CTRL); + WARN_ON(cor < 0); + +- /* MADC_ISR1 */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x61, cor) < 0); +- +- /* MADC_ISR2 */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x63, cor) < 0); ++ /* Clear TWL4030 MADC ISRs */ ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, ++ TWL4030_MADC_ISR1, cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, ++ TWL4030_MADC_ISR2, cor) < 0); + + /* key Pad */ +- /* KEYPAD - IMR1 */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x12) < 0); ++ /* Mask keypad interrupts at TWL4030 */ ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, ++ TWL4030_KEYPAD_KEYP_IMR1) < 0); ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, ++ TWL4030_KEYPAD_KEYP_IMR2) < 0); + + /* Are keypad interrupt status bits cleared by reads or writes? */ + cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD, + TWL4030_KEYPAD_KEYP_SIH_CTRL); + WARN_ON(cor < 0); + +- /* KEYPAD - ISR1 */ ++ /* Clear TWL4030 keypad ISRs */ + /* XXX does this still need to be done twice for some reason? */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x11, cor) < 0); +- +- /* KEYPAD - IMR2 */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x14) < 0); +- +- /* KEYPAD - ISR2 */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x13, cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, ++ TWL4030_KEYPAD_KEYP_ISR1, cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, ++ TWL4030_KEYPAD_KEYP_ISR2, cor) < 0); + + /* Slave address 0x49 */ +- /* GPIO_IMR1A */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1c) < 0); +- +- /* GPIO_IMR2A */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1d) < 0); +- +- /* GPIO_IMR3A */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1e) < 0); +- +- /* GPIO_IMR1B */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x22) < 0); + +- /* GPIO_IMR2B */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x23) < 0); +- +- /* GPIO_IMR3B */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x24) < 0); ++ /* Mask GPIO interrupts at TWL4030 */ ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, ++ REG_GPIO_IMR1A) < 0); ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, ++ REG_GPIO_IMR2A) < 0); ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, ++ REG_GPIO_IMR3A) < 0); ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, ++ REG_GPIO_IMR1B) < 0); ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, ++ REG_GPIO_IMR2B) < 0); ++ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, ++ REG_GPIO_IMR3B) < 0); + + /* Are GPIO interrupt status bits cleared by reads or writes? */ + cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO, +- TWL4030_GPIO_GPIO_SIH_CTRL); ++ REG_GPIO_SIH_CTRL); + WARN_ON(cor < 0); + +- /* GPIO_ISR1A */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x19, cor) < 0); +- +- /* GPIO_ISR2A */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1a, cor) < 0); +- +- /* GPIO_ISR3A */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1b, cor) < 0); +- +- /* GPIO_ISR1B */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1f, cor) < 0); +- +- /* GPIO_ISR2B */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x20, cor) < 0); +- +- /* GPIO_ISR3B */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x21, cor) < 0); ++ /* Clear TWL4030 GPIO ISRs */ ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1A, ++ cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2A, ++ cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3A, ++ cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1B, ++ cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2B, ++ cor) < 0); ++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3B, ++ cor) < 0); + + /* install an irq handler for each of the PIH modules */ + for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) { diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-09.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-09.patch new file mode 100644 index 0000000..ab6cc6d --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-09.patch @@ -0,0 +1,341 @@ +TWL4030: convert early interrupt mask/clear funcs to use array + +From: Paul Walmsley <paul@pwsan.com> + +Mask/clear TWL module IMRs/ISRs by iterating through arrays rather than +using a block of cut-and-pasted commands. Removes 1056 bytes of bloat. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + drivers/i2c/chips/twl4030-core.c | 302 +++++++++++++++++++++++--------------- + 1 files changed, 180 insertions(+), 122 deletions(-) + +diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c +index 38c227a..776b1dd 100644 +--- a/drivers/i2c/chips/twl4030-core.c ++++ b/drivers/i2c/chips/twl4030-core.c +@@ -160,6 +160,136 @@ + + #define TWL4030_SIH_CTRL_COR_MASK (1 << 2) + ++/** ++ * struct twl4030_mod_iregs - TWL module IMR/ISR regs to mask/clear at init ++ * @mod_no: TWL4030 module number (e.g., TWL4030_MODULE_GPIO) ++ * @sih_ctrl: address of module SIH_CTRL register ++ * @reg_cnt: number of IMR/ISR regs ++ * @imrs: pointer to array of TWL module interrupt mask register indices ++ * @isrs: pointer to array of TWL module interrupt status register indices ++ * ++ * Ties together TWL4030 modules and lists of IMR/ISR registers to mask/clear ++ * during twl_init_irq(). ++ */ ++struct twl4030_mod_iregs { ++ const u8 mod_no; ++ const u8 sih_ctrl; ++ const u8 reg_cnt; ++ const u8 *imrs; ++ const u8 *isrs; ++}; ++ ++/* TWL4030 INT module interrupt mask registers */ ++static const u8 __initconst twl4030_int_imr_regs[] = { ++ TWL4030_INT_PWR_IMR1, ++ TWL4030_INT_PWR_IMR2, ++}; ++ ++/* TWL4030 INT module interrupt status registers */ ++static const u8 __initconst twl4030_int_isr_regs[] = { ++ TWL4030_INT_PWR_ISR1, ++ TWL4030_INT_PWR_ISR2, ++}; ++ ++/* TWL4030 INTERRUPTS module interrupt mask registers */ ++static const u8 __initconst twl4030_interrupts_imr_regs[] = { ++ TWL4030_INTERRUPTS_BCIIMR1A, ++ TWL4030_INTERRUPTS_BCIIMR1B, ++ TWL4030_INTERRUPTS_BCIIMR2A, ++ TWL4030_INTERRUPTS_BCIIMR2B, ++}; ++ ++/* TWL4030 INTERRUPTS module interrupt status registers */ ++static const u8 __initconst twl4030_interrupts_isr_regs[] = { ++ TWL4030_INTERRUPTS_BCIISR1A, ++ TWL4030_INTERRUPTS_BCIISR1B, ++ TWL4030_INTERRUPTS_BCIISR2A, ++ TWL4030_INTERRUPTS_BCIISR2B, ++}; ++ ++/* TWL4030 MADC module interrupt mask registers */ ++static const u8 __initconst twl4030_madc_imr_regs[] = { ++ TWL4030_MADC_IMR1, ++ TWL4030_MADC_IMR2, ++}; ++ ++/* TWL4030 MADC module interrupt status registers */ ++static const u8 __initconst twl4030_madc_isr_regs[] = { ++ TWL4030_MADC_ISR1, ++ TWL4030_MADC_ISR2, ++}; ++ ++/* TWL4030 keypad module interrupt mask registers */ ++static const u8 __initconst twl4030_keypad_imr_regs[] = { ++ TWL4030_KEYPAD_KEYP_IMR1, ++ TWL4030_KEYPAD_KEYP_IMR2, ++}; ++ ++/* TWL4030 keypad module interrupt status registers */ ++static const u8 __initconst twl4030_keypad_isr_regs[] = { ++ TWL4030_KEYPAD_KEYP_ISR1, ++ TWL4030_KEYPAD_KEYP_ISR2, ++}; ++ ++/* TWL4030 GPIO module interrupt mask registers */ ++static const u8 __initconst twl4030_gpio_imr_regs[] = { ++ REG_GPIO_IMR1A, ++ REG_GPIO_IMR1B, ++ REG_GPIO_IMR2A, ++ REG_GPIO_IMR2B, ++ REG_GPIO_IMR3A, ++ REG_GPIO_IMR3B, ++}; ++ ++/* TWL4030 GPIO module interrupt status registers */ ++static const u8 __initconst twl4030_gpio_isr_regs[] = { ++ REG_GPIO_ISR1A, ++ REG_GPIO_ISR1B, ++ REG_GPIO_ISR2A, ++ REG_GPIO_ISR2B, ++ REG_GPIO_ISR3A, ++ REG_GPIO_ISR3B, ++}; ++ ++/* TWL4030 modules that have IMR/ISR registers that must be masked/cleared */ ++static const struct twl4030_mod_iregs __initconst twl4030_mod_regs[] = { ++ { ++ .mod_no = TWL4030_MODULE_INT, ++ .sih_ctrl = TWL4030_INT_PWR_SIH_CTRL, ++ .reg_cnt = ARRAY_SIZE(twl4030_int_imr_regs), ++ .imrs = twl4030_int_imr_regs, ++ .isrs = twl4030_int_isr_regs, ++ }, ++ { ++ .mod_no = TWL4030_MODULE_INTERRUPTS, ++ .sih_ctrl = TWL4030_INTERRUPTS_BCISIHCTRL, ++ .reg_cnt = ARRAY_SIZE(twl4030_interrupts_imr_regs), ++ .imrs = twl4030_interrupts_imr_regs, ++ .isrs = twl4030_interrupts_isr_regs, ++ }, ++ { ++ .mod_no = TWL4030_MODULE_MADC, ++ .sih_ctrl = TWL4030_MADC_MADC_SIH_CTRL, ++ .reg_cnt = ARRAY_SIZE(twl4030_madc_imr_regs), ++ .imrs = twl4030_madc_imr_regs, ++ .isrs = twl4030_madc_isr_regs, ++ }, ++ { ++ .mod_no = TWL4030_MODULE_KEYPAD, ++ .sih_ctrl = TWL4030_KEYPAD_KEYP_SIH_CTRL, ++ .reg_cnt = ARRAY_SIZE(twl4030_keypad_imr_regs), ++ .imrs = twl4030_keypad_imr_regs, ++ .isrs = twl4030_keypad_isr_regs, ++ }, ++ { ++ .mod_no = TWL4030_MODULE_GPIO, ++ .sih_ctrl = REG_GPIO_SIH_CTRL, ++ .reg_cnt = ARRAY_SIZE(twl4030_gpio_imr_regs), ++ .imrs = twl4030_gpio_imr_regs, ++ .isrs = twl4030_gpio_isr_regs, ++ }, ++}; ++ + + /* Helper functions */ + static int +@@ -779,136 +909,64 @@ static int twl4030_read_cor_bit(u8 mod_no, u8 reg) + return tmp; + } + ++/** ++ * twl4030_mask_clear_intrs - mask and clear all TWL4030 interrupts ++ * @t: pointer to twl4030_mod_iregs array ++ * @t_sz: ARRAY_SIZE(t) (starting at 1) ++ * ++ * Mask all TWL4030 interrupt mask registers (IMRs) and clear all ++ * interrupt status registers (ISRs). No return value, but will WARN if ++ * any I2C operations fail. ++ */ ++static void __init twl4030_mask_clear_intrs(const struct twl4030_mod_iregs *t, ++ const u8 t_sz) ++{ ++ int i, j; ++ ++ /* ++ * N.B. - further efficiency is possible here. Eight I2C ++ * operations on BCI and GPIO modules are avoidable if I2C ++ * burst read/write transactions were implemented. Would ++ * probably save about 1ms of boot time and a small amount of ++ * power. ++ */ ++ for (i = 0; i < t_sz; i++) { ++ const struct twl4030_mod_iregs tmr = t[i]; ++ ++ for (j = 0; j < tmr.reg_cnt; j++) { ++ int cor; ++ ++ /* Mask interrupts at the TWL4030 */ ++ WARN_ON(twl4030_i2c_write_u8(tmr.mod_no, 0xff, ++ tmr.imrs[j]) < 0); ++ ++ /* Are ISRs cleared by reads or writes? */ ++ cor = twl4030_read_cor_bit(tmr.mod_no, tmr.sih_ctrl); ++ WARN_ON(cor < 0); ++ ++ /* Clear TWL4030 ISRs */ ++ WARN_ON(twl4030_i2c_clear_isr(tmr.mod_no, ++ tmr.isrs[j], cor) < 0); ++ } ++ } ++ ++ return; ++} ++ ++ + static void twl_init_irq(void) + { +- int i = 0; ++ int i; + int res = 0; +- int cor; + char *msg = "Unable to register interrupt subsystem"; + unsigned int irq_num; + + /* +- * For each TWL4030 module with ISR/IMR registers, mask all +- * interrupts and then clear any existing interrupt status bits, +- * since we initially do not have any TWL4030 module interrupt +- * handlers present. ++ * Mask and clear all TWL4030 interrupts since initially we do ++ * not have any TWL4030 module interrupt handlers present + */ +- +- /* Mask INT (PWR) interrupts at TWL4030 */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, +- TWL4030_INT_PWR_IMR1) < 0); +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, +- TWL4030_INT_PWR_IMR2) < 0); +- +- /* Are PWR interrupt status bits cleared by reads or writes? */ +- cor = twl4030_read_cor_bit(TWL4030_MODULE_INT, +- TWL4030_INT_PWR_SIH_CTRL); +- WARN_ON(cor < 0); +- +- /* Clear TWL4030 INT (PWR) ISRs */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, +- TWL4030_INT_PWR_ISR1, cor) < 0); +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, +- TWL4030_INT_PWR_ISR2, cor) < 0); +- +- /* Slave address 0x4A */ +- +- /* Mask BCI interrupts at TWL4030 */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, +- TWL4030_INTERRUPTS_BCIIMR1A) < 0); +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, +- TWL4030_INTERRUPTS_BCIIMR2A) < 0); +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, +- TWL4030_INTERRUPTS_BCIIMR1B) < 0); +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, +- TWL4030_INTERRUPTS_BCIIMR2B) < 0); +- +- /* Are BCI interrupt status bits cleared by reads or writes? */ +- cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS, +- TWL4030_INTERRUPTS_BCISIHCTRL); +- WARN_ON(cor < 0); +- +- /* Clear TWL4030 BCI ISRs */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, +- TWL4030_INTERRUPTS_BCIISR1A, cor) < 0); +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, +- TWL4030_INTERRUPTS_BCIISR2A, cor) < 0); +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, +- TWL4030_INTERRUPTS_BCIISR1B, cor) < 0); +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, +- TWL4030_INTERRUPTS_BCIISR2B, cor) < 0); +- +- /* MAD C */ +- /* Mask MADC interrupts at TWL4030 */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, +- TWL4030_MADC_IMR1) < 0); +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, +- TWL4030_MADC_IMR2) < 0); +- +- /* Are MADC interrupt status bits cleared by reads or writes? */ +- cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC, +- TWL4030_MADC_MADC_SIH_CTRL); +- WARN_ON(cor < 0); +- +- /* Clear TWL4030 MADC ISRs */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, +- TWL4030_MADC_ISR1, cor) < 0); +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, +- TWL4030_MADC_ISR2, cor) < 0); +- +- /* key Pad */ +- /* Mask keypad interrupts at TWL4030 */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, +- TWL4030_KEYPAD_KEYP_IMR1) < 0); +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, +- TWL4030_KEYPAD_KEYP_IMR2) < 0); +- +- /* Are keypad interrupt status bits cleared by reads or writes? */ +- cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD, +- TWL4030_KEYPAD_KEYP_SIH_CTRL); +- WARN_ON(cor < 0); +- +- /* Clear TWL4030 keypad ISRs */ +- /* XXX does this still need to be done twice for some reason? */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, +- TWL4030_KEYPAD_KEYP_ISR1, cor) < 0); +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, +- TWL4030_KEYPAD_KEYP_ISR2, cor) < 0); +- +- /* Slave address 0x49 */ +- +- /* Mask GPIO interrupts at TWL4030 */ +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, +- REG_GPIO_IMR1A) < 0); +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, +- REG_GPIO_IMR2A) < 0); +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, +- REG_GPIO_IMR3A) < 0); +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, +- REG_GPIO_IMR1B) < 0); +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, +- REG_GPIO_IMR2B) < 0); +- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, +- REG_GPIO_IMR3B) < 0); +- +- /* Are GPIO interrupt status bits cleared by reads or writes? */ +- cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO, +- REG_GPIO_SIH_CTRL); +- WARN_ON(cor < 0); +- +- /* Clear TWL4030 GPIO ISRs */ +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1A, +- cor) < 0); +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2A, +- cor) < 0); +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3A, +- cor) < 0); +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1B, +- cor) < 0); +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2B, +- cor) < 0); +- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3B, +- cor) < 0); ++ twl4030_mask_clear_intrs(twl4030_mod_regs, ++ ARRAY_SIZE(twl4030_mod_regs)); + + /* install an irq handler for each of the PIH modules */ + for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) { diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/cache-display-fix.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/cache-display-fix.patch new file mode 100644 index 0000000..c96b95f --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/cache-display-fix.patch @@ -0,0 +1,238 @@ +On Tue, 2008-07-01 at 06:23 +0100, Dirk Behme wrote: +> Catalin Marinas wrote: +> > But, anyway, if you want a patch, Harry is updating it to a recent +> > kernel. +> +> Any news on this? I think there are some people wanting a patch ;) + +See below for a preliminary patch updated to 2.6.26-rc8. Note that I +don't plan to submit it in its current form but clean it up a bit first. + + +Show the cache type of ARMv7 CPUs + +From: Catalin Marinas <catalin.marinas@arm.com> + +Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> +--- + + arch/arm/kernel/setup.c | 137 +++++++++++++++++++++++++++++++++++++++++++++- + include/asm-arm/system.h | 18 ++++++ + 2 files changed, 153 insertions(+), 2 deletions(-) + + +diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c +index 5ae0eb2..0cd238d 100644 +--- a/arch/arm/kernel/setup.c ++++ b/arch/arm/kernel/setup.c +@@ -256,6 +256,24 @@ static const char *proc_arch[] = { + "?(17)", + }; + ++static const char *v7_cache_policy[4] = { ++ "reserved", ++ "AVIVT", ++ "VIPT", ++ "PIPT", ++}; ++ ++static const char *v7_cache_type[8] = { ++ "none", ++ "instruction only", ++ "data only", ++ "separate instruction and data", ++ "unified", ++ "unknown type", ++ "unknown type", ++ "unknown type", ++}; ++ + #define CACHE_TYPE(x) (((x) >> 25) & 15) + #define CACHE_S(x) ((x) & (1 << 24)) + #define CACHE_DSIZE(x) (((x) >> 12) & 4095) /* only if S=1 */ +@@ -266,6 +284,22 @@ static const char *proc_arch[] = { + #define CACHE_M(y) ((y) & (1 << 2)) + #define CACHE_LINE(y) ((y) & 3) + ++#define CACHE_TYPE_V7(x) (((x) >> 14) & 3) ++#define CACHE_UNIFIED(x) ((((x) >> 27) & 7)+1) ++#define CACHE_COHERENT(x) ((((x) >> 24) & 7)+1) ++ ++#define CACHE_ID_LEVEL_MASK 7 ++#define CACHE_ID_LEVEL_BITS 3 ++ ++#define CACHE_LINE_V7(v) ((1 << (((v) & 7)+4))) ++#define CACHE_ASSOC_V7(v) ((((v) >> 3) & ((1<<10)-1))+1) ++#define CACHE_SETS_V7(v) ((((v) >> 13) & ((1<<15)-1))+1) ++#define CACHE_SIZE_V7(v) (CACHE_LINE_V7(v)*CACHE_ASSOC_V7(v)*CACHE_SETS_V7(v)) ++#define CACHE_WA_V7(v) (((v) & (1<<28)) != 0) ++#define CACHE_RA_V7(v) (((v) & (1<<29)) != 0) ++#define CACHE_WB_V7(v) (((v) & (1<<30)) != 0) ++#define CACHE_WT_V7(v) (((v) & (1<<31)) != 0) ++ + static inline void dump_cache(const char *prefix, int cpu, unsigned int cache) + { + unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0); +@@ -279,11 +313,57 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache) + CACHE_LINE(cache))); + } + ++static void dump_v7_cache(const char *type, int cpu, unsigned int level) ++{ ++ unsigned int cachesize; ++ ++ write_extended_cpuid(2,0,0,0,level); /* Set the cache size selection register */ ++ write_extended_cpuid(0,7,5,4,0); /* Prefetch flush to wait for above */ ++ cachesize = read_extended_cpuid(1,0,0,0); ++ ++ printk("CPU%u: %s cache: %d bytes, associativity %d, %d byte lines, %d sets,\n supports%s%s%s%s\n", ++ cpu, type, ++ CACHE_SIZE_V7(cachesize),CACHE_ASSOC_V7(cachesize), ++ CACHE_LINE_V7(cachesize),CACHE_SETS_V7(cachesize), ++ CACHE_WA_V7(cachesize) ? " WA" : "", ++ CACHE_RA_V7(cachesize) ? " RA" : "", ++ CACHE_WB_V7(cachesize) ? " WB" : "", ++ CACHE_WT_V7(cachesize) ? " WT" : ""); ++} ++ + static void __init dump_cpu_info(int cpu) + { + unsigned int info = read_cpuid(CPUID_CACHETYPE); + +- if (info != processor_id) { ++ if (info != processor_id && (info & (1 << 31))) { ++ /* ARMv7 style of cache info register */ ++ unsigned int id = read_extended_cpuid(1,0,0,1); ++ unsigned int level = 0; ++ printk("CPU%u: L1 I %s cache. Caches unified at level %u, coherent at level %u\n", ++ cpu, ++ v7_cache_policy[CACHE_TYPE_V7(info)], ++ CACHE_UNIFIED(id), ++ CACHE_COHERENT(id)); ++ ++ while (id & CACHE_ID_LEVEL_MASK) { ++ printk("CPU%u: Level %u cache is %s\n", ++ cpu, (level >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]); ++ ++ if (id & 1) { ++ /* Dump I at this level */ ++ dump_v7_cache("I", cpu, level | 1); ++ } ++ ++ if (id & (4 | 2)) { ++ /* Dump D or unified at this level */ ++ dump_v7_cache((id & 4) ? "unified" : "D", cpu, level); ++ } ++ ++ /* Next level out */ ++ level += 2; ++ id >>= CACHE_ID_LEVEL_BITS; ++ } ++ } else if (info != processor_id) { + printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT", + cache_types[CACHE_TYPE(info)]); + if (CACHE_S(info)) { +@@ -916,6 +996,30 @@ c_show_cache(struct seq_file *m, const char *type, unsigned int cache) + CACHE_LINE(cache))); + } + ++static void c_show_v7_cache(struct seq_file *m, const char *type, unsigned int levelselect) ++{ ++ unsigned int cachesize; ++ unsigned int level = (levelselect >> 1) + 1; ++ ++ write_extended_cpuid(2,0,0,0,levelselect); /* Set the cache size selection register */ ++ write_extended_cpuid(0,7,5,4,0); /* Prefetch flush to wait for above */ ++ cachesize = read_extended_cpuid(1,0,0,0); ++ ++ seq_printf(m, "L%u %s size\t\t: %d bytes\n" ++ "L%u %s assoc\t\t: %d\n" ++ "L%u %s line length\t: %d\n" ++ "L%u %s sets\t\t: %d\n" ++ "L%u %s supports\t\t:%s%s%s%s\n", ++ level, type, CACHE_SIZE_V7(cachesize), ++ level, type, CACHE_ASSOC_V7(cachesize), ++ level, type, CACHE_LINE_V7(cachesize), ++ level, type, CACHE_SETS_V7(cachesize), ++ level, type, CACHE_WA_V7(cachesize) ? " WA" : "", ++ CACHE_RA_V7(cachesize) ? " RA" : "", ++ CACHE_WB_V7(cachesize) ? " WB" : "", ++ CACHE_WT_V7(cachesize) ? " WT" : ""); ++} ++ + static int c_show(struct seq_file *m, void *v) + { + int i; +@@ -971,7 +1075,36 @@ static int c_show(struct seq_file *m, void *v) + + { + unsigned int cache_info = read_cpuid(CPUID_CACHETYPE); +- if (cache_info != processor_id) { ++ if (cache_info != processor_id && (cache_info & (1<<31))) { ++ /* V7 style of cache info register */ ++ unsigned int id = read_extended_cpuid(1,0,0,1); ++ unsigned int levelselect = 0; ++ seq_printf(m, "L1 I cache\t:%s\n" ++ "Cache unification level\t: %u\n" ++ "Cache coherency level\t: %u\n", ++ v7_cache_policy[CACHE_TYPE_V7(cache_info)], ++ CACHE_UNIFIED(id), ++ CACHE_COHERENT(id)); ++ ++ while (id & CACHE_ID_LEVEL_MASK) { ++ seq_printf(m, "Level %u cache\t\t: %s\n", ++ (levelselect >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]); ++ ++ if (id & 1) { ++ /* Dump I at this level */ ++ c_show_v7_cache(m, "I", levelselect | 1); ++ } ++ ++ if (id & (4 | 2)) { ++ /* Dump D or unified at this level */ ++ c_show_v7_cache(m, (id & 4) ? "cache" : "D", levelselect); ++ } ++ ++ /* Next level out */ ++ levelselect += 2; ++ id >>= CACHE_ID_LEVEL_BITS; ++ } ++ } else if (cache_info != processor_id) { + seq_printf(m, "Cache type\t: %s\n" + "Cache clean\t: %s\n" + "Cache lockdown\t: %s\n" +diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h +index 514af79..704738e 100644 +--- a/include/asm-arm/system.h ++++ b/include/asm-arm/system.h +@@ -74,6 +74,24 @@ + : "cc"); \ + __val; \ + }) ++#define read_extended_cpuid(op1,op2,op3,op4) \ ++ ({ \ ++ unsigned int __val; \ ++ asm("mrc p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4) \ ++ : "=r" (__val) \ ++ : \ ++ : "cc"); \ ++ __val; \ ++ }) ++ ++#define write_extended_cpuid(op1,op2,op3,op4,v) \ ++ ({ \ ++ unsigned int __val = v; \ ++ asm("mcr p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4) \ ++ : \ ++ : "r" (__val) \ ++ : "cc"); \ ++ }) + #else + extern unsigned int processor_id; + #define read_cpuid(reg) (processor_id) + + +-- +Catalin + + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/defconfig b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/defconfig new file mode 100644 index 0000000..0adc452 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/defconfig @@ -0,0 +1,1983 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-omap1 +# Wed Jul 30 14:28:15 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_OPROFILE_ARMV7=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_MARKERS is not set +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_LSF=y +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y +# CONFIG_ARCH_MSM7X00A is not set + +# +# TI OMAP Implementations +# +CONFIG_ARCH_OMAP_OTG=y +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_OMAP2 is not set +CONFIG_ARCH_OMAP3=y + +# +# OMAP Feature Selections +# +# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set +# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set +CONFIG_OMAP_SMARTREFLEX=y +# CONFIG_OMAP_SMARTREFLEX_TESTING is not set +CONFIG_OMAP_RESET_CLOCKS=y +CONFIG_OMAP_BOOT_TAG=y +CONFIG_OMAP_BOOT_REASON=y +# CONFIG_OMAP_COMPONENT_VERSION is not set +# CONFIG_OMAP_GPIO_SWITCH is not set +# CONFIG_OMAP_MUX is not set +CONFIG_OMAP_MCBSP=y +# CONFIG_OMAP_MMU_FWK is not set +# CONFIG_OMAP_MBOX_FWK is not set +# CONFIG_OMAP_MPU_TIMER is not set +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_32K_TIMER_HZ=128 +CONFIG_OMAP_DM_TIMER=y +# CONFIG_OMAP_LL_DEBUG_UART1 is not set +# CONFIG_OMAP_LL_DEBUG_UART2 is not set +CONFIG_OMAP_LL_DEBUG_UART3=y +CONFIG_ARCH_OMAP34XX=y +CONFIG_ARCH_OMAP3430=y + +# +# OMAP Board Type +# +# CONFIG_MACH_OMAP_LDP is not set +# CONFIG_MACH_OMAP_3430SDP is not set +# CONFIG_MACH_OMAP3EVM is not set +CONFIG_MACH_OMAP3_BEAGLE=y + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_IFAR=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=128 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_LEDS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE=" debug " +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPUIdle +# + +# +# CPU idle PM support +# +CONFIG_CPU_IDLE=y + +# +# Governors +# +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +CONFIG_NEON_CACHE_BUG=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +CONFIG_NET_SCH_FIFO=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIUSB=y +CONFIG_BT_HCIUSB_SCO=y +CONFIG_BT_HCIBTSDIO=y +# CONFIG_BT_HCIUART is not set +CONFIG_BT_HCIBCM203X=y +CONFIG_BT_HCIBPA10X=y +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIBRF6150 is not set +# CONFIG_BT_HCIH4P is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_NL80211=y +CONFIG_WIRELESS_EXT=y +CONFIG_MAC80211=y + +# +# Rate control algorithm selection +# +CONFIG_MAC80211_RC_DEFAULT_PID=y +# CONFIG_MAC80211_RC_DEFAULT_NONE is not set + +# +# Selecting 'y' for an algorithm will +# + +# +# build the algorithm into mac80211. +# +CONFIG_MAC80211_RC_DEFAULT="pid" +CONFIG_MAC80211_RC_PID=y +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set +# CONFIG_MAC80211_DEBUG is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_OMAP2=y +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_OMAP_STI is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_RAID5_RESHAPE=y +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m +# CONFIG_DM_MULTIPATH_RDAC is not set +# CONFIG_DM_MULTIPATH_HP is not set +CONFIG_DM_DELAY=m +# CONFIG_DM_UEVENT is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +CONFIG_DUMMY=m +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_MII=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +# CONFIG_LIBERTAS_SDIO is not set +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_USB_ZD1201=m +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8187 is not set +# CONFIG_P54_COMMON is not set +# CONFIG_IWLWIFI_LEDS is not set +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_ZD1211RW is not set +# CONFIG_RT2X00 is not set + +# +# USB Network Adapters +# +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_CDCETHER=y +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_OMAP=y +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_PCA_PLATFORM is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +CONFIG_SENSORS_EEPROM=y +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_ISP1301_OMAP is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_TLV320AIC23 is not set +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_GPIO=y +CONFIG_TWL4030_MADC=m +CONFIG_TWL4030_USB=y +CONFIG_TWL4030_USB_HS_ULPI=y +CONFIG_TWL4030_PWRBUTTON=y +CONFIG_TWL4030_POWEROFF=y +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_LP5521 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_OMAP24XX is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +CONFIG_SPI_TSC2101=y +CONFIG_SPI_TSC2102=y +# CONFIG_SPI_TSC210X is not set +# CONFIG_SPI_TSC2301 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_HAVE_GPIO_LIB=y + +# +# GPIO Support +# +# CONFIG_DEBUG_GPIO is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=m +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_BQ27x00 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_TSC210X is not set +CONFIG_SENSORS_OMAP34XX=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_OMAP_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_DVB_CORE=m +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_TUNER=m +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_CX25840=m +CONFIG_VIDEO_CX2341X=m +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_TUNER_3036 is not set +# CONFIG_VIDEO_AU0828 is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +# CONFIG_VIDEO_EM28XX is not set +CONFIG_VIDEO_USBVISION=m +CONFIG_VIDEO_USBVIDEO=m +CONFIG_USB_VICAM=m +CONFIG_USB_IBMCAM=m +CONFIG_USB_KONICAWC=m +CONFIG_USB_QUICKCAM_MESSENGER=m +# CONFIG_USB_ET61X251 is not set +CONFIG_VIDEO_OVCAMCHIP=m +CONFIG_USB_W9968CF=m +CONFIG_USB_OV511=m +CONFIG_USB_SE401=m +CONFIG_USB_SN9C102=m +CONFIG_USB_STV680=m +# CONFIG_USB_ZC0301 is not set +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_ZR364XX=m +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_TEA5761 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_USB_SI470X is not set +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set + +# +# Supported USB Adapters +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_DVB_CINERGYT2=m +# CONFIG_DVB_CINERGYT2_TUNING is not set + +# +# Supported FlexCopII (B2C2) Adapters +# +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_TDA10048=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_S5H1411=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_LNBP21=m +# CONFIG_DVB_ISL6405 is not set +CONFIG_DVB_ISL6421=m +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +CONFIG_FB_OMAP=y +# CONFIG_FB_OMAP_031M3R is not set +# CONFIG_FB_OMAP_048M3R is not set +CONFIG_FB_OMAP_079M3R=y +# CONFIG_FB_OMAP_092M9R is not set +# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set +# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set +CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=8 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# ALSA ARM devices +# +# CONFIG_SND_OMAP_AIC23 is not set +# CONFIG_SND_OMAP_TSC2101 is not set +# CONFIG_SND_SX1 is not set +# CONFIG_SND_OMAP_TSC2102 is not set +# CONFIG_SND_OMAP24XX_EAC is not set + +# +# SPI devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y + +# +# System on Chip audio support +# +CONFIG_SND_SOC=y + +# +# ALSA SoC audio for Freescale SOCs +# + +# +# SoC Audio for the Texas Instruments OMAP +# +CONFIG_SND_OMAP_SOC=y +CONFIG_SND_OMAP_SOC_MCBSP=y +CONFIG_SND_OMAP_SOC_OMAP3BEAGLE=y +CONFIG_SND_SOC_TWL4030=y + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_OMAP_EHCI_PHY_MODE=y +# CONFIG_OMAP_EHCI_TLL_MODE is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_SOC=y + +# +# OMAP 343x high speed USB support +# +# CONFIG_USB_MUSB_HOST is not set +# CONFIG_USB_MUSB_PERIPHERAL is not set +CONFIG_USB_MUSB_OTG=y +CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_USB_MUSB_HDRC_HCD=y +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_MUSB_LOGLEVEL=0 + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +# CONFIG_USB_EZUSB is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_AIRPRIME is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP2101 is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +# CONFIG_USB_BERRY_CHARGE is not set +CONFIG_USB_LED=m +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +CONFIG_USB_ETH=y +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=y +# CONFIG_MMC_TEST is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_OMAP_HS=y +CONFIG_MMC_SPI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_OMAP_DEBUG is not set +# CONFIG_LEDS_OMAP is not set +# CONFIG_LEDS_OMAP_PWM is not set +CONFIG_LEDS_GPIO=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +CONFIG_RTC_DRV_TWL4030=y +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_UIO is not set + +# +# CBUS support +# +# CONFIG_CBUS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_BIND34 is not set +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_CRYPTD=m +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=m +CONFIG_CRYPTO_XCBC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=m +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/flash.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/flash.patch new file mode 100644 index 0000000..4c76cd9 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/flash.patch @@ -0,0 +1,558 @@ +diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile +index 13d0043..d582b8f 100644 +--- a/arch/arm/mach-omap2/Makefile ++++ b/arch/arm/mach-omap2/Makefile +@@ -44,7 +44,8 @@ obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \ + board-omap3evm-flash.o + obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \ + usb-musb.o usb-ehci.o \ +- hsmmc.o ++ hsmmc.o \ ++ board-omap3beagle-flash.o + obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ + hsmmc.o \ + usb-musb.o +diff --git a/arch/arm/mach-omap2/board-omap3beagle-flash.c b/arch/arm/mach-omap2/board-omap3beagle-flash.c +new file mode 100644 +index 0000000..5346df0 +--- /dev/null ++++ b/arch/arm/mach-omap2/board-omap3beagle-flash.c +@@ -0,0 +1,119 @@ ++/* ++ * board-omap3beagle-flash.c ++ * ++ * Copyright (c) 2008 Texas Instruments ++ * ++ * Modified from board-omap3evm-flash.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/platform_device.h> ++#include <linux/mtd/mtd.h> ++#include <linux/mtd/partitions.h> ++#include <linux/mtd/nand.h> ++#include <linux/types.h> ++#include <linux/io.h> ++ ++#include <asm/mach/flash.h> ++#include <asm/arch/board.h> ++#include <asm/arch/gpmc.h> ++#include <asm/arch/nand.h> ++ ++#define GPMC_CS0_BASE 0x60 ++#define GPMC_CS_SIZE 0x30 ++ ++static struct mtd_partition omap3beagle_nand_partitions[] = { ++ /* All the partition sizes are listed in terms of NAND block size */ ++ { ++ .name = "X-Loader", ++ .offset = 0, ++ .size = 4*(64 * 2048), ++ .mask_flags = MTD_WRITEABLE, /* force read-only */ ++ }, ++ { ++ .name = "U-Boot", ++ .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ ++ .size = 15*(64 * 2048), ++ .mask_flags = MTD_WRITEABLE, /* force read-only */ ++ }, ++ { ++ .name = "U-Boot Env", ++ .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ ++ .size = 1*(64 * 2048), ++ }, ++ { ++ .name = "Kernel", ++ .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ ++ .size = 32*(64 * 2048), ++ }, ++ { ++ .name = "File System", ++ .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ ++ .size = MTDPART_SIZ_FULL, ++ }, ++}; ++ ++static struct omap_nand_platform_data omap3beagle_nand_data = { ++ .parts = omap3beagle_nand_partitions, ++ .nr_parts = ARRAY_SIZE(omap3beagle_nand_partitions), ++ .dma_channel = -1, /* disable DMA in OMAP NAND driver */ ++ .nand_setup = NULL, ++ .dev_ready = NULL, ++}; ++ ++static struct resource omap3beagle_nand_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device omap3beagle_nand_device = { ++ .name = "omap2-nand", ++ .id = -1, ++ .dev = { ++ .platform_data = &omap3beagle_nand_data, ++ }, ++ .num_resources = 1, ++ .resource = &omap3beagle_nand_resource, ++}; ++ ++ ++void __init omap3beagle_flash_init(void) ++{ ++ u8 cs = 0; ++ u8 nandcs = GPMC_CS_NUM + 1; ++ ++ u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; ++ ++ /* find out the chip-select on which NAND exists */ ++ while (cs < GPMC_CS_NUM) { ++ u32 ret = 0; ++ ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); ++ ++ if ((ret & 0xC00) == 0x800) { ++ printk(KERN_INFO "Found NAND on CS%d\n", cs); ++ if (nandcs > GPMC_CS_NUM) ++ nandcs = cs; ++ } ++ cs++; ++ } ++ ++ if (nandcs > GPMC_CS_NUM) { ++ printk(KERN_INFO "NAND: Unable to find configuration " ++ "in GPMC\n "); ++ return; ++ } ++ ++ if (nandcs < GPMC_CS_NUM) { ++ omap3beagle_nand_data.cs = nandcs; ++ omap3beagle_nand_data.gpmc_cs_baseaddr = (void *)(gpmc_base_add + ++ GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); ++ omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add); ++ ++ printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); ++ if (platform_device_register(&omap3beagle_nand_device) < 0) ++ printk(KERN_ERR "Unable to register NAND device\n"); ++ } ++} +diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c +index c992cc7..99e042e 100644 +--- a/arch/arm/mach-omap2/board-omap3beagle.c ++++ b/arch/arm/mach-omap2/board-omap3beagle.c +@@ -94,6 +94,7 @@ static void __init omap3_beagle_init(void) + hsmmc_init(); + usb_musb_init(); + usb_ehci_init(); ++ omap3beagle_flash_init(); + } + + arch_initcall(omap3_beagle_i2c_init); +diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig +index 3d5e432..02b9ced 100644 +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -71,7 +71,7 @@ config MTD_NAND_AMS_DELTA + + config MTD_NAND_OMAP2 + tristate "NAND Flash device on OMAP 2420H4/2430SDP boards" +- depends on (ARM && ARCH_OMAP2 && MTD_NAND) ++ depends on ARM && MTD_NAND && (ARCH_OMAP2 || ARCH_OMAP3) + help + Support for NAND flash on Texas Instruments 2430SDP/2420H4 platforms. + +diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c +index 3b7307c..3aac1d2 100644 +--- a/drivers/mtd/nand/omap2.c ++++ b/drivers/mtd/nand/omap2.c +@@ -111,15 +111,6 @@ + static const char *part_probes[] = { "cmdlinepart", NULL }; + #endif + +-static int hw_ecc = 1; +- +-/* new oob placement block for use with hardware ecc generation */ +-static struct nand_ecclayout omap_hw_eccoob = { +- .eccbytes = 12, +- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, +- .oobfree = {{16, 32}, {33, 63} }, +-}; +- + struct omap_nand_info { + struct nand_hw_control controller; + struct omap_nand_platform_data *pdata; +@@ -133,6 +124,13 @@ struct omap_nand_info { + void __iomem *gpmc_cs_baseaddr; + void __iomem *gpmc_baseaddr; + }; ++ ++/* ++ * omap_nand_wp - This function enable or disable the Write Protect feature on ++ * NAND device ++ * @mtd: MTD device structure ++ * @mode: WP ON/OFF ++ */ + static void omap_nand_wp(struct mtd_info *mtd, int mode) + { + struct omap_nand_info *info = container_of(mtd, +@@ -189,11 +187,11 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) + } + + /* +-* omap_read_buf - read data from NAND controller into buffer +-* @mtd: MTD device structure +-* @buf: buffer to store date +-* @len: number of bytes to read +-*/ ++ * omap_read_buf - read data from NAND controller into buffer ++ * @mtd: MTD device structure ++ * @buf: buffer to store date ++ * @len: number of bytes to read ++ */ + static void omap_read_buf(struct mtd_info *mtd, u_char *buf, int len) + { + struct omap_nand_info *info = container_of(mtd, +@@ -207,11 +205,11 @@ static void omap_read_buf(struct mtd_info *mtd, u_char *buf, int len) + } + + /* +-* omap_write_buf - write buffer to NAND controller +-* @mtd: MTD device structure +-* @buf: data buffer +-* @len: number of bytes to write +-*/ ++ * omap_write_buf - write buffer to NAND controller ++ * @mtd: MTD device structure ++ * @buf: data buffer ++ * @len: number of bytes to write ++ */ + static void omap_write_buf(struct mtd_info *mtd, const u_char * buf, int len) + { + struct omap_nand_info *info = container_of(mtd, +@@ -250,10 +248,16 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) + return 0; + } + ++#ifdef CONFIG_MTD_NAND_OMAP_HWECC ++/* ++ * omap_hwecc_init-Initialize the Hardware ECC for NAND flash in GPMC controller ++ * @mtd: MTD device structure ++ */ + static void omap_hwecc_init(struct mtd_info *mtd) + { + struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, + mtd); ++ register struct nand_chip *chip = mtd->priv; + unsigned long val = 0x0; + + /* Read from ECC Control Register */ +@@ -264,16 +268,15 @@ static void omap_hwecc_init(struct mtd_info *mtd) + + /* Read from ECC Size Config Register */ + val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG); +- /* ECCSIZE1=512 | ECCSIZE0=8bytes | Select eccResultsize[0123] */ +- val = ((0x000000FF<<22) | (0x00000003<<12) | (0x0000000F)); ++ /* ECCSIZE1=512 | Select eccResultsize[0-3] */ ++ val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F)); + __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG); +- +- + } + + /* +- * This function will generate true ECC value, which can be used ++ * gen_true_ecc - This function will generate true ECC value, which can be used + * when correcting data read from NAND flash memory core ++ * @ecc_buf: buffer to store ecc code + */ + static void gen_true_ecc(u8 *ecc_buf) + { +@@ -289,8 +292,12 @@ static void gen_true_ecc(u8 *ecc_buf) + } + + /* +- * This function compares two ECC's and indicates if there is an error. +- * If the error can be corrected it will be corrected to the buffer ++ * omap_compare_ecc - This function compares two ECC's and indicates if there ++ * is an error. If the error can be corrected it will be corrected to the ++ * buffer ++ * @ecc_data1: ecc code from nand spare area ++ * @ecc_data2: ecc code from hardware register obtained from hardware ecc ++ * @page_data: page data + */ + static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ + u8 *ecc_data2, /* read from register */ +@@ -409,6 +416,14 @@ static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ + } + } + ++/* ++ * omap_correct_data - Compares the ecc read from nand spare area with ECC ++ * registers values and corrects one bit error if it has occured ++ * @mtd: MTD device structure ++ * @dat: page data ++ * @read_ecc: ecc read from nand flash ++ * @calc_ecc: ecc read from ECC registers ++ */ + static int omap_correct_data(struct mtd_info *mtd, u_char * dat, + u_char * read_ecc, u_char * calc_ecc) + { +@@ -436,65 +451,64 @@ static int omap_correct_data(struct mtd_info *mtd, u_char * dat, + } + + /* +-** Generate non-inverted ECC bytes. +-** +-** Using noninverted ECC can be considered ugly since writing a blank +-** page ie. padding will clear the ECC bytes. This is no problem as long +-** nobody is trying to write data on the seemingly unused page. +-** +-** Reading an erased page will produce an ECC mismatch between +-** generated and read ECC bytes that has to be dealt with separately. +-*/ ++ * omap_calcuate_ecc - Generate non-inverted ECC bytes. ++ * Using noninverted ECC can be considered ugly since writing a blank ++ * page ie. padding will clear the ECC bytes. This is no problem as long ++ * nobody is trying to write data on the seemingly unused page. Reading ++ * an erased page will produce an ECC mismatch between generated and read ++ * ECC bytes that has to be dealt with separately. ++ * @mtd: MTD device structure ++ * @dat: The pointer to data on which ecc is computed ++ * @ecc_code: The ecc_code buffer ++ */ + static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) + { + struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, + mtd); + unsigned long val = 0x0; +- unsigned long reg, n; +- +- /* Ex NAND_ECC_HW12_2048 */ +- if ((info->nand.ecc.mode == NAND_ECC_HW) && +- (info->nand.ecc.size == 2048)) +- n = 4; +- else +- n = 1; ++ unsigned long reg; + + /* Start Reading from HW ECC1_Result = 0x200 */ + reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT); +- while (n--) { +- val = __raw_readl(reg); +- *ecc_code++ = val; /* P128e, ..., P1e */ +- *ecc_code++ = val >> 16; /* P128o, ..., P1o */ +- /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ +- *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); +- reg += 4; +- } ++ val = __raw_readl(reg); ++ *ecc_code++ = val; /* P128e, ..., P1e */ ++ *ecc_code++ = val >> 16; /* P128o, ..., P1o */ ++ /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ ++ *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); ++ reg += 4; + + return 0; +-} /* omap_calculate_ecc */ ++} + ++/* ++ * omap_enable_hwecc - This function enables the hardware ecc functionality ++ * @mtd: MTD device structure ++ * @mode: Read/Write mode ++ */ + static void omap_enable_hwecc(struct mtd_info *mtd, int mode) + { + struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, + mtd); ++ register struct nand_chip *chip = mtd->priv; ++ unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; + unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG); + + switch (mode) { + case NAND_ECC_READ : + __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL); +- /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */ +- val = (1 << 7) | (0x0) | (0x1) ; ++ /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ ++ val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); + break; + case NAND_ECC_READSYN : +- __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL); +- /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */ +- val = (1 << 7) | (0x0) | (0x1) ; ++ __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL); ++ /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ ++ val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); + break; + case NAND_ECC_WRITE : + __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL); +- /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */ +- val = (1 << 7) | (0x0) | (0x1) ; ++ /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ ++ val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); + break; + default: + DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n", +@@ -504,7 +518,38 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode) + + __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG); + } ++#endif + ++/* ++ * omap_wait - Wait function is called during Program and erase ++ * operations and the way it is called from MTD layer, we should wait ++ * till the NAND chip is ready after the programming/erase operation ++ * has completed. ++ * @mtd: MTD device structure ++ * @chip: NAND Chip structure ++ */ ++static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) ++{ ++ register struct nand_chip *this = mtd->priv; ++ struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, ++ mtd); ++ int status = 0; ++ ++ this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr + ++ GPMC_CS_NAND_COMMAND; ++ this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA; ++ ++ while (!(status & 0x40)) { ++ __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W); ++ status = __raw_readb(this->IO_ADDR_R); ++ } ++ return status; ++} ++ ++/* ++ * omap_dev_ready - calls the platform specific dev_ready function ++ * @mtd: MTD device structure ++ */ + static int omap_dev_ready(struct mtd_info *mtd) + { + struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, +@@ -534,7 +579,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) + struct omap_nand_info *info; + struct omap_nand_platform_data *pdata; + int err; +- unsigned long val; ++ unsigned long val; + + + pdata = pdev->dev.platform_data; +@@ -568,15 +613,20 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) + } + + /* Enable RD PIN Monitoring Reg */ +- val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1); +- val |= WR_RD_PIN_MONITORING; +- gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val); ++ if (pdata->dev_ready) { ++ val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1); ++ val |= WR_RD_PIN_MONITORING; ++ gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val); ++ } + + val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7); + val &= ~(0xf << 8); + val |= (0xc & 0xf) << 8; + gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val); + ++ /* NAND write protect off */ ++ omap_nand_wp(&info->mtd, NAND_WP_OFF); ++ + if (!request_mem_region(info->phys_base, NAND_IO_SIZE, + pdev->dev.driver->name)) { + err = -EBUSY; +@@ -597,29 +647,39 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) + info->nand.write_buf = omap_write_buf; + info->nand.verify_buf = omap_verify_buf; + +- info->nand.dev_ready = omap_dev_ready; +- info->nand.chip_delay = 0; +- +- /* Options */ +- info->nand.options = NAND_BUSWIDTH_16; +- info->nand.options |= NAND_SKIP_BBTSCAN; +- +- if (hw_ecc) { +- /* init HW ECC */ +- omap_hwecc_init(&info->mtd); +- +- info->nand.ecc.calculate = omap_calculate_ecc; +- info->nand.ecc.hwctl = omap_enable_hwecc; +- info->nand.ecc.correct = omap_correct_data; +- info->nand.ecc.mode = NAND_ECC_HW; +- info->nand.ecc.bytes = 12; +- info->nand.ecc.size = 2048; +- info->nand.ecc.layout = &omap_hw_eccoob; +- ++ /* ++ * If RDY/BSY line is connected to OMAP then use the omap ready funcrtion ++ * and the generic nand_wait function which reads the status register ++ * after monitoring the RDY/BSY line.Otherwise use a standard chip delay ++ * which is slightly more than tR (AC Timing) of the NAND device and read ++ * status register until you get a failure or success ++ */ ++ if (pdata->dev_ready) { ++ info->nand.dev_ready = omap_dev_ready; ++ info->nand.chip_delay = 0; + } else { +- info->nand.ecc.mode = NAND_ECC_SOFT; ++ info->nand.waitfunc = omap_wait; ++ info->nand.chip_delay = 50; + } + ++ info->nand.options |= NAND_SKIP_BBTSCAN; ++ if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000) ++ == 0x1000) ++ info->nand.options |= NAND_BUSWIDTH_16; ++ ++#ifdef CONFIG_MTD_NAND_OMAP_HWECC ++ info->nand.ecc.bytes = 3; ++ info->nand.ecc.size = 512; ++ info->nand.ecc.calculate = omap_calculate_ecc; ++ info->nand.ecc.hwctl = omap_enable_hwecc; ++ info->nand.ecc.correct = omap_correct_data; ++ info->nand.ecc.mode = NAND_ECC_HW; ++ ++ /* init HW ECC */ ++ omap_hwecc_init(&info->mtd); ++#else ++ info->nand.ecc.mode = NAND_ECC_SOFT; ++#endif + + /* DIP switches on some boards change between 8 and 16 bit + * bus widths for flash. Try the other width if the first try fails. +@@ -636,14 +696,12 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) + err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0); + if (err > 0) + add_mtd_partitions(&info->mtd, info->parts, err); +- else if (err < 0 && pdata->parts) ++ else if (err <= 0 && pdata->parts) + add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts); + else + #endif + add_mtd_device(&info->mtd); + +- omap_nand_wp(&info->mtd, NAND_WP_OFF); +- + platform_set_drvdata(pdev, &info->mtd); + + return 0; +diff --git a/include/asm-arm/arch-omap/board-omap3beagle.h b/include/asm-arm/arch-omap/board-omap3beagle.h +index 46dff31..26ecfb8 100644 +--- a/include/asm-arm/arch-omap/board-omap3beagle.h ++++ b/include/asm-arm/arch-omap/board-omap3beagle.h +@@ -29,5 +29,7 @@ + #ifndef __ASM_ARCH_OMAP3_BEAGLE_H + #define __ASM_ARCH_OMAP3_BEAGLE_H + ++extern void omap3beagle_flash_init(void); ++ + #endif /* __ASM_ARCH_OMAP3_BEAGLE_H */ + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/i2c-omap-race-fix.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/i2c-omap-race-fix.diff new file mode 100644 index 0000000..6eb33f7 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/i2c-omap-race-fix.diff @@ -0,0 +1,118 @@ +From linux-omap-owner@vger.kernel.org Tue Jul 15 21:23:13 2008 +Received: from localhost + ([127.0.0.1] helo=dominion ident=koen) + by dominion.dominion.void with esmtp (Exim 4.69) + (envelope-from <linux-omap-owner@vger.kernel.org>) + id 1KIq7E-0004FX-VS + for koen@localhost; Tue, 15 Jul 2008 21:23:13 +0200 +Received: from xs.service.utwente.nl [130.89.5.250] + by dominion with POP3 (fetchmail-6.3.6) + for <koen@localhost> (single-drop); Tue, 15 Jul 2008 21:23:12 +0200 (CEST) +Received: from mail.service.utwente.nl ([130.89.5.254]) by exchange.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 15 Jul 2008 21:01:02 +0200 +Received: from mx.utwente.nl ([130.89.2.12]) by mail.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 15 Jul 2008 21:01:01 +0200 +Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) + by mx.utwente.nl (8.12.10/SuSE Linux 0.7) with ESMTP id m6FJ0qDf031889 + for <k.kooi@student.utwente.nl>; Tue, 15 Jul 2008 21:00:52 +0200 +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1756776AbYGOTAV (ORCPT <rfc822;k.kooi@student.utwente.nl>); + Tue, 15 Jul 2008 15:00:21 -0400 +Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755065AbYGOTAV + (ORCPT <rfc822;linux-omap-outgoing>); + Tue, 15 Jul 2008 15:00:21 -0400 +Received: from utopia.booyaka.com ([72.9.107.138]:35569 "EHLO + utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1756776AbYGOTAU (ORCPT + <rfc822;linux-omap@vger.kernel.org>); Tue, 15 Jul 2008 15:00:20 -0400 +Received: (qmail 2982 invoked by uid 526); 15 Jul 2008 19:00:18 -0000 +Date: Tue, 15 Jul 2008 13:00:18 -0600 (MDT) +From: Paul Walmsley <paul@pwsan.com> +To: linux-omap@vger.kernel.org +Subject: [PATCH] i2c-omap: close suspected race between omap_i2c_idle() and + omap_i2c_isr() +Message-ID: <alpine.DEB.1.00.0807151259180.467@utopia.booyaka.com> +User-Agent: Alpine 1.00 (DEB 882 2007-12-20) +MIME-Version: 1.0 +Content-Type: TEXT/PLAIN; charset=US-ASCII +Sender: linux-omap-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-omap.vger.kernel.org> +X-Mailing-List: linux-omap@vger.kernel.org +X-UTwente-MailScanner-Information: Scanned by MailScanner. Contact servicedesk@icts.utwente.nl for more information. +X-UTwente-MailScanner: Found to be clean +X-UTwente-MailScanner-From: linux-omap-owner@vger.kernel.org +X-Spam-Status: No +X-OriginalArrivalTime: 15 Jul 2008 19:01:01.0610 (UTC) FILETIME=[1FBA68A0:01C8E6AD] + + +omap_i2c_idle() sets an internal flag, "dev->idle", instructing its +ISR to decline interrupts. It sets this flag before it actually masks +the interrupts on the I2C controller. This is problematic, since an +I2C interrupt could arrive after dev->idle is set, but before the +interrupt source is masked. When this happens, Linux disables the I2C +controller's IRQ, causing all future transactions on the bus to fail. + +Symptoms, happening on about 7% of boots: + + irq 56: nobody cared (try booting with the "irqpoll" option) + <warning traceback here> + Disabling IRQ #56 + i2c_omap i2c_omap.1: controller timed out + +In omap_i2c_idle(), this patch sets dev->idle only after the interrupt +mask write to the I2C controller has left the ARM write buffer. +That's probably the major offender. For additional prophylaxis, in +omap_i2c_unidle(), the patch clears the dev->idle flag before +interrupts are enabled, rather than afterwards. + +The patch has survived twenty-two reboots on the 3430SDP here without +wedging I2C1. Not absolutely dispositive, but promising! + + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + drivers/i2c/busses/i2c-omap.c | 10 ++++++++-- + 1 files changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c +index 55779f5..ed7e9ad 100644 +--- a/drivers/i2c/busses/i2c-omap.c ++++ b/drivers/i2c/busses/i2c-omap.c +@@ -209,22 +209,28 @@ static void omap_i2c_unidle(struct omap_i2c_dev *dev) + if (dev->iclk != NULL) + clk_enable(dev->iclk); + clk_enable(dev->fclk); ++ dev->idle = 0; + if (dev->iestate) + omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); +- dev->idle = 0; + } + + static void omap_i2c_idle(struct omap_i2c_dev *dev) + { + u16 iv; + +- dev->idle = 1; + dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); + omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); + if (dev->rev1) + iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); + else + omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate); ++ /* ++ * The wmb() is to ensure that the I2C interrupt mask write ++ * reaches the I2C controller before the dev->idle store ++ * occurs. ++ */ ++ wmb(); ++ dev->idle = 1; + clk_disable(dev->fclk); + if (dev->iclk != NULL) + clk_disable(dev->iclk); +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/logo_linux_clut224.ppm b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/logo_linux_clut224.ppm new file mode 100644 index 0000000..d29fc1c --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/logo_linux_clut224.ppm @@ -0,0 +1,73147 @@ +P3 +# CREATOR: GIMP PNM Filter Version 1.1 +387 63 +255 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 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+0 diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks1.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks1.diff new file mode 100644 index 0000000..d7dadbc --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks1.diff @@ -0,0 +1,25 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Tue, 22 Jul 2008 00:31:11 +0000 (+0100) +Subject: ARM: OMAP: make dpll4_m4_ck programmable with clk_set_rate() +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=2b7b958dc79e51127d7a4ecf88ce12dbc6c31426 + +ARM: OMAP: make dpll4_m4_ck programmable with clk_set_rate() + +Filling the set_rate and round_rate fields of dpll4_m4_ck makes +this clock programmable through clk_set_rate(). This is needed +to give omapfb control over the dss1_alwon_fck rate. +--- + +diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h +index 161da12..876eb13 100644 +--- a/arch/arm/mach-omap2/clock34xx.h ++++ b/arch/arm/mach-omap2/clock34xx.h +@@ -815,6 +815,8 @@ static struct clk dpll4_m4_ck = { + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, ++ .set_rate = &omap2_clksel_set_rate, ++ .round_rate = &omap2_clksel_round_rate, + }; + + /* The PWRDN bit is apparently only available on 3430ES2 and above */ diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks2.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks2.diff new file mode 100644 index 0000000..c8b370d --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks2.diff @@ -0,0 +1,62 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Tue, 22 Jul 2008 00:58:18 +0000 (+0100) +Subject: ARM: OMAP: add clk_get_parent() for OMAP2/3 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=e2de5e5578fbaa9b4b75074796da0608fc93e6ae + +ARM: OMAP: add clk_get_parent() for OMAP2/3 + +Signed-off-by: Mans Rullgard <mans@mansr.com> +--- + +diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c +index 577be44..28aec36 100644 +--- a/arch/arm/mach-omap2/clock.c ++++ b/arch/arm/mach-omap2/clock.c +@@ -824,6 +824,11 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) + return 0; + } + ++struct clk *omap2_clk_get_parent(struct clk *clk) ++{ ++ return clk->parent; ++} ++ + /* DPLL rate rounding code */ + + /** +diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h +index 49245f7..4aa69d5 100644 +--- a/arch/arm/mach-omap2/clock.h ++++ b/arch/arm/mach-omap2/clock.h +@@ -29,6 +29,7 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate); + int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); + int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); + long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); ++struct clk *omap2_clk_get_parent(struct clk *clk); + + #ifdef CONFIG_OMAP_RESET_CLOCKS + void omap2_clk_disable_unused(struct clk *clk); +diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c +index 54cc6e1..ed7af21 100644 +--- a/arch/arm/mach-omap2/clock24xx.c ++++ b/arch/arm/mach-omap2/clock24xx.c +@@ -422,6 +422,7 @@ static struct clk_functions omap2_clk_functions = { + .clk_round_rate = omap2_clk_round_rate, + .clk_set_rate = omap2_clk_set_rate, + .clk_set_parent = omap2_clk_set_parent, ++ .clk_get_parent = omap2_clk_get_parent, + .clk_disable_unused = omap2_clk_disable_unused, + #ifdef CONFIG_CPU_FREQ + .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, +diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c +index 04dedec..08c8c46 100644 +--- a/arch/arm/mach-omap2/clock34xx.c ++++ b/arch/arm/mach-omap2/clock34xx.c +@@ -541,6 +541,7 @@ static struct clk_functions omap2_clk_functions = { + .clk_round_rate = omap2_clk_round_rate, + .clk_set_rate = omap2_clk_set_rate, + .clk_set_parent = omap2_clk_set_parent, ++ .clk_get_parent = omap2_clk_get_parent, + .clk_disable_unused = omap2_clk_disable_unused, + }; + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks3.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks3.diff new file mode 100644 index 0000000..f8407fc --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks3.diff @@ -0,0 +1,94 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Wed, 23 Jul 2008 08:40:07 +0000 (+0100) +Subject: ARM: OMAP: Set DSS1_ALWON_FCLK to a multiple of the pixel clock +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=01ee28c50701caa94739e764c3dae9298edd8216 + +ARM: OMAP: Set DSS1_ALWON_FCLK to a multiple of the pixel clock + +This sets the DSS1_ALWON_FCLK clock as close as possible to a +multiple of the requested pixel clock, while keeping it below +the 173MHz limit. + +Due to of the structure of the clock tree, dss1_alwon_fck cannot +be set directly, and we must use dpll4_m4_ck instead. + +Signed-off-by: Mans Rullgard <mans@mansr.com> +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index fd06ca2..e0e8528 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -176,6 +176,7 @@ static struct { + + struct clk *dss_ick, *dss1_fck; + struct clk *dss_54m_fck; ++ struct clk *dpll4_m4_ck; + + enum omapfb_update_mode update_mode; + struct omapfb_device *fbdev; +@@ -738,21 +739,34 @@ static void setup_color_conv_coef(void) + MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range); + } + +-#define MAX_FCK_LCD 173000000 ++#define MAX_FCK 173000000 + + static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div) + { ++ unsigned long prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck)); ++ unsigned long pcd_min = is_tft? 2: 3; ++ unsigned long fck_div; + unsigned long fck, lck; + + pck = max(1, pck); ++ ++ if (pck * pcd_min > MAX_FCK) { ++ dev_warn(dispc.fbdev->dev, "pixclock %d kHz too high.\n", ++ pck / 1000); ++ pck = MAX_FCK / pcd_min; ++ } ++ ++ fck = pck * 2; ++ fck_div = (prate + pck) / fck; ++ if (fck_div > 16) ++ fck_div /= (fck_div + 15) / 16; ++ if (fck_div < 1) ++ fck_div = 1; ++ clk_set_rate(dispc.dpll4_m4_ck, prate / fck_div); + fck = clk_get_rate(dispc.dss1_fck); +- *lck_div = (fck + MAX_FCK_LCD - 1) / MAX_FCK_LCD; +- lck = fck / *lck_div; +- *pck_div = (lck + pck - 1) / pck; +- if (is_tft) +- *pck_div = max(2, *pck_div); +- else +- *pck_div = max(3, *pck_div); ++ ++ *lck_div = 1; ++ *pck_div = (fck + pck - 1) / pck; + if (*pck_div > 255) { + *pck_div = 255; + lck = pck * *pck_div; +@@ -914,11 +928,21 @@ static int get_dss_clocks(void) + return PTR_ERR(dispc.dss_54m_fck); + } + ++ if (IS_ERR((dispc.dpll4_m4_ck = ++ clk_get(dispc.fbdev->dev, "dpll4_m4_ck")))) { ++ dev_err(dispc.fbdev->dev, "can't get dpll4_m4_ck"); ++ clk_put(dispc.dss_ick); ++ clk_put(dispc.dss1_fck); ++ clk_put(dispc.dss_54m_fck); ++ return PTR_ERR(dispc.dss_54m_fck); ++ } ++ + return 0; + } + + static void put_dss_clocks(void) + { ++ clk_put(dispc.dpll4_m4_ck); + clk_put(dispc.dss_54m_fck); + clk_put(dispc.dss1_fck); + clk_put(dispc.dss_ick); diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/no-cortex-deadlock.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/no-cortex-deadlock.patch new file mode 100644 index 0000000..32ec4c2 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/no-cortex-deadlock.patch @@ -0,0 +1,75 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Wed, 30 Jul 2008 08:25:51 +0000 (+0100) +Subject: ARM: NEON L1 cache bug workaround (erratum 451034) +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=26023493baf13e0a67fd6cf08d87be5ff6f7c56d + +ARM: NEON L1 cache bug workaround (erratum 451034) + +On Cortex-A8 r1p0 and r1p1, executing a NEON store with an integer +store in the store buffer, can cause a processor deadlock under +certain conditions. + +Executing a DMB instruction before saving NEON/VFP registers and before +return to userspace makes it safe to run code which includes similar +counter-measures. Userspace code can still trigger the deadlock, so +a different workaround is required to safely run untrusted code. + +See ARM Cortex-A8 Errata Notice (PR120-PRDC-008070) for full details. +--- + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 8c75840..1172e14 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1071,6 +1071,22 @@ config NEON + Say Y to include support code for NEON, the ARMv7 Advanced SIMD + Extension. + ++config NEON_CACHE_BUG ++ bool "NEON L1 cache bug workaround (erratum 451034)" ++ depends on VFPv3 ++ help ++ On Cortex-A8 r1p0 and r1p1, executing a NEON store with an integer ++ store in the store buffer, can cause a processor deadlock under ++ certain conditions. ++ ++ See ARM Cortex-A8 Errata Notice (PR120-PRDC-008070) for full details. ++ ++ Say Y to include a workaround. ++ ++ WARNING: Even with this option enabled, userspace code can trigger ++ the deadlock. To safely run untrusted code, a different fix is ++ required. ++ + endmenu + + menu "Userspace binary formats" +diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S +index 597ed00..e50094e 100644 +--- a/arch/arm/kernel/entry-common.S ++++ b/arch/arm/kernel/entry-common.S +@@ -68,6 +68,10 @@ no_work_pending: + /* perform architecture specific actions before user return */ + arch_ret_to_user r1, lr + ++#ifdef CONFIG_NEON_CACHE_BUG ++ dmb ++#endif ++ + @ slow_restore_user_regs + ldr r1, [sp, #S_PSR] @ get calling cpsr + ldr lr, [sp, #S_PC]! @ get pc +diff --git a/include/asm-arm/vfpmacros.h b/include/asm-arm/vfpmacros.h +index cccb389..c9d2976 100644 +--- a/include/asm-arm/vfpmacros.h ++++ b/include/asm-arm/vfpmacros.h +@@ -32,6 +32,9 @@ + + @ write all the working registers out of the VFP + .macro VFPFSTMIA, base, tmp ++#ifdef CONFIG_NEON_CACHE_BUG ++ dmb ++#endif + #if __LINUX_ARM_ARCH__ < 6 + STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15} + #else diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/no-empty-flash-warnings.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/no-empty-flash-warnings.patch new file mode 100644 index 0000000..ab344b0 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/no-empty-flash-warnings.patch @@ -0,0 +1,15 @@ +diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c +index 1d437de..33b3feb 100644 +--- a/fs/jffs2/scan.c ++++ b/fs/jffs2/scan.c +@@ -647,8 +647,8 @@ scan_more: + inbuf_ofs = ofs - buf_ofs; + while (inbuf_ofs < scan_end) { + if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) { +- printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", +- empty_start, ofs); ++// printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", ++// empty_start, ofs); + if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start))) + return err; + goto scan_more; diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/no-harry-potter.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/no-harry-potter.diff new file mode 100644 index 0000000..2bb20ab --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/no-harry-potter.diff @@ -0,0 +1,11 @@ +--- /tmp/Makefile 2008-04-24 14:36:20.509598016 +0200 ++++ git/arch/arm/Makefile 2008-04-24 14:36:31.949546584 +0200 +@@ -47,7 +47,7 @@ + # Note that GCC does not numerically define an architecture version + # macro, but instead defines a whole series of macros which makes + # testing for a specific architecture or later rather impossible. +-arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a) ++arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a) + arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6) + # Only override the compiler option if ARMv6. The ARMv6K extensions are + # always available in ARMv7 diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch new file mode 100644 index 0000000..25e5aad --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch @@ -0,0 +1,114 @@ +From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008 +Received: from localhost + ([127.0.0.1] helo=dominion ident=koen) + by dominion.dominion.void with esmtp (Exim 4.63) + (envelope-from <linux-omap-owner@vger.kernel.org>) + id 1KB2tB-0005XT-FQ + for koen@localhost; Tue, 24 Jun 2008 09:24:30 +0200 +Received: from xs.service.utwente.nl [130.89.5.250] + by dominion with POP3 (fetchmail-6.3.6) + for <koen@localhost> (single-drop); Tue, 24 Jun 2008 09:24:29 +0200 (CEST) +Received: from mail.service.utwente.nl ([130.89.5.254]) by exchange.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 24 Jun 2008 09:13:04 +0200 +Received: from mx.utwente.nl ([130.89.2.13]) by mail.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 24 Jun 2008 09:13:03 +0200 +Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) + by mx.utwente.nl (8.12.10/SuSE Linux 0.7) with ESMTP id m5O7CcD7008917 + for <k.kooi@student.utwente.nl>; Tue, 24 Jun 2008 09:12:38 +0200 +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1751623AbYFXHMh (ORCPT <rfc822;k.kooi@student.utwente.nl>); + Tue, 24 Jun 2008 03:12:37 -0400 +Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751670AbYFXHMh + (ORCPT <rfc822;linux-omap-outgoing>); + Tue, 24 Jun 2008 03:12:37 -0400 +Received: from utopia.booyaka.com ([72.9.107.138]:47392 "EHLO + utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1751623AbYFXHMg (ORCPT + <rfc822;linux-omap@vger.kernel.org>); Tue, 24 Jun 2008 03:12:36 -0400 +Received: (qmail 1797 invoked by uid 526); 24 Jun 2008 07:12:35 -0000 +Date: Tue, 24 Jun 2008 01:12:35 -0600 (MDT) +From: Paul Walmsley <paul@pwsan.com> +To: linux-omap@vger.kernel.org +Subject: [PATCH] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4 +Message-ID: <alpine.DEB.1.00.0806240111320.9741@utopia.booyaka.com> +User-Agent: Alpine 1.00 (DEB 882 2007-12-20) +MIME-Version: 1.0 +Content-Type: TEXT/PLAIN; charset=US-ASCII +Sender: linux-omap-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-omap.vger.kernel.org> +X-Mailing-List: linux-omap@vger.kernel.org +X-UTwente-MailScanner-Information: Scanned by MailScanner. Contact servicedesk@icts.utwente.nl for more information. +X-UTwente-MailScanner: Found to be clean +X-UTwente-MailScanner-From: linux-omap-owner@vger.kernel.org +X-Spam-Status: No +X-OriginalArrivalTime: 24 Jun 2008 07:13:04.0264 (UTC) FILETIME=[BE950880:01C8D5C9] + + +OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and +DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this +into the OMAP3 clock framework. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + arch/arm/mach-omap2/clock34xx.h | 20 ++++++++++++++++---- + 1 files changed, 16 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h +index b4dceea..9605744 100644 +--- a/arch/arm/mach-omap2/clock34xx.h ++++ b/arch/arm/mach-omap2/clock34xx.h +@@ -1029,8 +1029,15 @@ static struct clk corex2_fck = { + + /* DPLL power domain clock controls */ + +-static const struct clksel div2_core_clksel[] = { +- { .parent = &core_ck, .rates = div2_rates }, ++static const struct clksel_rate div4_rates[] = { ++ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, ++ { .div = 2, .val = 2, .flags = RATE_IN_343X }, ++ { .div = 4, .val = 4, .flags = RATE_IN_343X }, ++ { .div = 0 } ++}; ++ ++static const struct clksel div4_core_clksel[] = { ++ { .parent = &core_ck, .rates = div4_rates }, + { .parent = NULL } + }; + +@@ -1044,7 +1051,7 @@ static struct clk dpll1_fck = { + .init = &omap2_init_clksel_parent, + .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, +- .clksel = div2_core_clksel, ++ .clksel = div4_core_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +@@ -1119,7 +1126,7 @@ static struct clk dpll2_fck = { + .init = &omap2_init_clksel_parent, + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, +- .clksel = div2_core_clksel, ++ .clksel = div4_core_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +@@ -1155,6 +1162,11 @@ static struct clk iva2_ck = { + + /* Common interface clocks */ + ++static const struct clksel div2_core_clksel[] = { ++ { .parent = &core_ck, .rates = div2_rates }, ++ { .parent = NULL } ++}; ++ + static struct clk l3_ick = { + .name = "l3_ick", + .parent = &core_ck, +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/omap3-jitter.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/omap3-jitter.patch new file mode 100644 index 0000000..2e0dfd9 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/omap3-jitter.patch @@ -0,0 +1,95 @@ +From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008 +Received: from localhost + ([127.0.0.1] helo=dominion ident=koen) + by dominion.dominion.void with esmtp (Exim 4.63) + (envelope-from <linux-omap-owner@vger.kernel.org>) + id 1KB2tC-0005XT-Mj + for koen@localhost; Tue, 24 Jun 2008 09:24:30 +0200 +Received: from xs.service.utwente.nl [130.89.5.250] + by dominion with POP3 (fetchmail-6.3.6) + for <koen@localhost> (single-drop); Tue, 24 Jun 2008 09:24:30 +0200 (CEST) +Received: from mail.service.utwente.nl ([130.89.5.253]) by exchange.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 24 Jun 2008 09:20:48 +0200 +Received: from smtp.utwente.nl ([130.89.2.8]) by mail.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 24 Jun 2008 09:20:47 +0200 +Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) + by smtp.utwente.nl (8.12.10/SuSE Linux 0.7) with ESMTP id m5O7BPWU031214 + for <k.kooi@student.utwente.nl>; Tue, 24 Jun 2008 09:11:25 +0200 +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1751128AbYFXHLY (ORCPT <rfc822;k.kooi@student.utwente.nl>); + Tue, 24 Jun 2008 03:11:24 -0400 +Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751405AbYFXHLX + (ORCPT <rfc822;linux-omap-outgoing>); + Tue, 24 Jun 2008 03:11:23 -0400 +Received: from utopia.booyaka.com ([72.9.107.138]:44580 "EHLO + utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1751128AbYFXHLX (ORCPT + <rfc822;linux-omap@vger.kernel.org>); Tue, 24 Jun 2008 03:11:23 -0400 +Received: (qmail 1744 invoked by uid 526); 24 Jun 2008 07:11:21 -0000 +Date: Tue, 24 Jun 2008 01:11:21 -0600 (MDT) +From: Paul Walmsley <paul@pwsan.com> +To: linux-omap@vger.kernel.org +Subject: [PATCH] OMAP3 clock: fix DPLL jitter correction and rate + programming +Message-ID: <alpine.DEB.1.00.0806240109440.9741@utopia.booyaka.com> +User-Agent: Alpine 1.00 (DEB 882 2007-12-20) +MIME-Version: 1.0 +Content-Type: TEXT/PLAIN; charset=US-ASCII +Sender: linux-omap-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-omap.vger.kernel.org> +X-Mailing-List: linux-omap@vger.kernel.org +X-UTwente-MailScanner-Information: Scanned by MailScanner. Contact servicedesk@icts.utwente.nl for more information. +X-UTwente-MailScanner: Found to be clean +X-UTwente-MailScanner-From: linux-omap-owner@vger.kernel.org +X-Spam-Status: No +X-OriginalArrivalTime: 24 Jun 2008 07:20:48.0265 (UTC) FILETIME=[D325F790:01C8D5CA] + + +Fix DPLL jitter correction programming. Previously, +omap3_noncore_dpll_program() stored the FREQSEL jitter correction +parameter to the wrong register. This caused jitter correction to be set +incorrectly and also caused the DPLL divider to be programmed incorrectly. + +Also, fix DPLL divider programming. An off-by-one error existed in +omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher +divider than intended. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + arch/arm/mach-omap2/clock34xx.c | 13 ++++++++----- + 1 files changed, 8 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c +index 408b51a..8fdf8f3 100644 +--- a/arch/arm/mach-omap2/clock34xx.c ++++ b/arch/arm/mach-omap2/clock34xx.c +@@ -346,14 +346,17 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) + /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ + _omap3_noncore_dpll_bypass(clk); + ++ /* Set jitter correction */ ++ v = __raw_readl(dd->control_reg); ++ v &= ~dd->freqsel_mask; ++ v |= freqsel << __ffs(dd->freqsel_mask); ++ __raw_writel(v, dd->control_reg); ++ ++ /* Set DPLL multiplier, divider */ + v = __raw_readl(dd->mult_div1_reg); + v &= ~(dd->mult_mask | dd->div1_mask); +- +- /* Set mult (M), div1 (N), freqsel */ + v |= m << __ffs(dd->mult_mask); +- v |= n << __ffs(dd->div1_mask); +- v |= freqsel << __ffs(dd->freqsel_mask); +- ++ v |= (n - 1) << __ffs(dd->div1_mask); + __raw_writel(v, dd->mult_div1_reg); + + /* We let the clock framework set the other output dividers later */ +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/oprofile-0.9.3.armv7.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/oprofile-0.9.3.armv7.diff new file mode 100644 index 0000000..dbc11fb --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/oprofile-0.9.3.armv7.diff @@ -0,0 +1,611 @@ +Hi, + +This patch adds Oprofile support on ARMv7, using the PMNC unit. +Tested on OMAP3430 SDP. + +Feedback and comments are welcome. + +The patch to user space components is attached for reference. It i applies +against version 0.9.3 of oprofile source +(http://prdownloads.sourceforge.net/oprofile/oprofile-0.9.3.tar.gz). + +Regards, +Jean. + +--- + +From: Jean Pihet <jpihet@mvista.com> +Date: Tue, 6 May 2008 17:21:44 +0200 +Subject: [PATCH] ARM: Add ARMv7 oprofile support + +Add ARMv7 Oprofile support to kernel + +Signed-off-by: Jean Pihet <jpihet@mvista.com> +--- + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index c60a27d..60b50a0 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -161,6 +161,11 @@ config OPROFILE_MPCORE + config OPROFILE_ARM11_CORE + bool + ++config OPROFILE_ARMV7 ++ def_bool y ++ depends on CPU_V7 && !SMP ++ bool ++ + endif + + config VECTORS_BASE +diff --git a/arch/arm/oprofile/Makefile b/arch/arm/oprofile/Makefile +index e61d0cc..88e31f5 100644 +--- a/arch/arm/oprofile/Makefile ++++ b/arch/arm/oprofile/Makefile +@@ -11,3 +11,4 @@ oprofile-$(CONFIG_CPU_XSCALE) += op_model_xscale.o + oprofile-$(CONFIG_OPROFILE_ARM11_CORE) += op_model_arm11_core.o + oprofile-$(CONFIG_OPROFILE_ARMV6) += op_model_v6.o + oprofile-$(CONFIG_OPROFILE_MPCORE) += op_model_mpcore.o ++oprofile-$(CONFIG_OPROFILE_ARMV7) += op_model_v7.o +diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c +index 0a5cf3a..3fcd752 100644 +--- a/arch/arm/oprofile/common.c ++++ b/arch/arm/oprofile/common.c +@@ -145,6 +145,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) + spec = &op_mpcore_spec; + #endif + ++#ifdef CONFIG_OPROFILE_ARMV7 ++ spec = &op_armv7_spec; ++#endif ++ + if (spec) { + ret = spec->init(); + if (ret < 0) +diff --git a/arch/arm/oprofile/op_arm_model.h +b/arch/arm/oprofile/op_arm_model.h +index 4899c62..8c4e4f6 100644 +--- a/arch/arm/oprofile/op_arm_model.h ++++ b/arch/arm/oprofile/op_arm_model.h +@@ -26,6 +26,7 @@ extern struct op_arm_model_spec op_xscale_spec; + + extern struct op_arm_model_spec op_armv6_spec; + extern struct op_arm_model_spec op_mpcore_spec; ++extern struct op_arm_model_spec op_armv7_spec; + + extern void arm_backtrace(struct pt_regs * const regs, unsigned int depth); + +diff --git a/arch/arm/oprofile/op_model_v7.c b/arch/arm/oprofile/op_model_v7.c +new file mode 100644 +index 0000000..a159bc1 +--- /dev/null ++++ b/arch/arm/oprofile/op_model_v7.c +@@ -0,0 +1,407 @@ ++/** ++ * @file op_model_v7.c ++ * ARM V7 (Cortex A8) Event Monitor Driver ++ * ++ * @remark Copyright 2008 Jean Pihet <jpihet@mvista.com> ++ * @remark Copyright 2004 ARM SMP Development Team ++ */ ++#include <linux/types.h> ++#include <linux/errno.h> ++#include <linux/oprofile.h> ++#include <linux/interrupt.h> ++#include <linux/irq.h> ++#include <linux/smp.h> ++ ++#include "op_counter.h" ++#include "op_arm_model.h" ++#include "op_model_v7.h" ++ ++/* #define DEBUG */ ++ ++ ++/* ++ * ARM V7 PMNC support ++ */ ++ ++static u32 cnt_en[CNTMAX]; ++ ++static inline void armv7_pmnc_write(u32 val) ++{ ++ val &= PMNC_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val)); ++} ++ ++static inline u32 armv7_pmnc_read(void) ++{ ++ u32 val; ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); ++ return val; ++} ++ ++static inline u32 armv7_pmnc_enable_counter(unsigned int cnt) ++{ ++ u32 val; ++ ++ if (cnt >= CNTMAX) { ++ printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter" ++ " %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ if (cnt == CCNT) ++ val = CNTENS_C; ++ else ++ val = (1 << (cnt - CNT0)); ++ ++ val &= CNTENS_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline u32 armv7_pmnc_disable_counter(unsigned int cnt) ++{ ++ u32 val; ++ ++ if (cnt >= CNTMAX) { ++ printk(KERN_ERR "oprofile: CPU%u disabling wrong PMNC counter" ++ " %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ if (cnt == CCNT) ++ val = CNTENC_C; ++ else ++ val = (1 << (cnt - CNT0)); ++ ++ val &= CNTENC_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline u32 armv7_pmnc_enable_intens(unsigned int cnt) ++{ ++ u32 val; ++ ++ if (cnt >= CNTMAX) { ++ printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter" ++ " interrupt enable %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ if (cnt == CCNT) ++ val = INTENS_C; ++ else ++ val = (1 << (cnt - CNT0)); ++ ++ val &= INTENS_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline u32 armv7_pmnc_getreset_flags(void) ++{ ++ u32 val; ++ ++ /* Read */ ++ asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); ++ ++ /* Write to clear flags */ ++ val &= FLAG_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); ++ ++ return val; ++} ++ ++static inline int armv7_pmnc_select_counter(unsigned int cnt) ++{ ++ u32 val; ++ ++ if ((cnt == CCNT) || (cnt >= CNTMAX)) { ++ printk(KERN_ERR "oprofile: CPU%u selecting wrong PMNC counteri" ++ " %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ val = (cnt - CNT0) & SELECT_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline void armv7_pmnc_write_evtsel(unsigned int cnt, u32 val) ++{ ++ if (armv7_pmnc_select_counter(cnt) == cnt) { ++ val &= EVTSEL_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); ++ } ++} ++ ++static void armv7_pmnc_reset_counter(unsigned int cnt) ++{ ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); ++ u32 val = -(u32)counter_config[cpu_cnt].count; ++ ++ switch (cnt) { ++ case CCNT: ++ armv7_pmnc_disable_counter(cnt); ++ ++ asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val)); ++ ++ if (cnt_en[cnt] != 0) ++ armv7_pmnc_enable_counter(cnt); ++ ++ break; ++ ++ case CNT0: ++ case CNT1: ++ case CNT2: ++ case CNT3: ++ armv7_pmnc_disable_counter(cnt); ++ ++ if (armv7_pmnc_select_counter(cnt) == cnt) ++ asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val)); ++ ++ if (cnt_en[cnt] != 0) ++ armv7_pmnc_enable_counter(cnt); ++ ++ break; ++ ++ default: ++ printk(KERN_ERR "oprofile: CPU%u resetting wrong PMNC counter" ++ " %d\n", smp_processor_id(), cnt); ++ break; ++ } ++} ++ ++int armv7_setup_pmnc(void) ++{ ++ unsigned int cnt; ++ ++ if (armv7_pmnc_read() & PMNC_E) { ++ printk(KERN_ERR "oprofile: CPU%u PMNC still enabled when setup" ++ " new event counter.\n", smp_processor_id()); ++ return -EBUSY; ++ } ++ ++ /* ++ * Initialize & Reset PMNC: C bit, D bit and P bit. ++ * Note: Using a slower count for CCNT (D bit: divide by 64) results ++ * in a more stable system ++ */ ++ armv7_pmnc_write(PMNC_P | PMNC_C | PMNC_D); ++ ++ ++ for (cnt = CCNT; cnt < CNTMAX; cnt++) { ++ unsigned long event; ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); ++ ++ /* ++ * Disable counter ++ */ ++ armv7_pmnc_disable_counter(cnt); ++ cnt_en[cnt] = 0; ++ ++ if (!counter_config[cpu_cnt].enabled) ++ continue; ++ ++ event = counter_config[cpu_cnt].event & 255; ++ ++ /* ++ * Set event (if destined for PMNx counters) ++ * We don't need to set the event if it's a cycle count ++ */ ++ if (cnt != CCNT) ++ armv7_pmnc_write_evtsel(cnt, event); ++ ++ /* ++ * Enable interrupt for this counter ++ */ ++ armv7_pmnc_enable_intens(cnt); ++ ++ /* ++ * Reset counter ++ */ ++ armv7_pmnc_reset_counter(cnt); ++ ++ /* ++ * Enable counter ++ */ ++ armv7_pmnc_enable_counter(cnt); ++ cnt_en[cnt] = 1; ++ } ++ ++ return 0; ++} ++ ++static inline void armv7_start_pmnc(void) ++{ ++ armv7_pmnc_write(armv7_pmnc_read() | PMNC_E); ++} ++ ++static inline void armv7_stop_pmnc(void) ++{ ++ armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E); ++} ++ ++/* ++ * CPU counters' IRQ handler (one IRQ per CPU) ++ */ ++static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg) ++{ ++ struct pt_regs *regs = get_irq_regs(); ++ unsigned int cnt; ++ u32 flags; ++ ++ ++ /* ++ * Stop IRQ generation ++ */ ++ armv7_stop_pmnc(); ++ ++ /* ++ * Get and reset overflow status flags ++ */ ++ flags = armv7_pmnc_getreset_flags(); ++ ++ /* ++ * Cycle counter ++ */ ++ if (flags & FLAG_C) { ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), CCNT); ++ armv7_pmnc_reset_counter(CCNT); ++ oprofile_add_sample(regs, cpu_cnt); ++ } ++ ++ /* ++ * PMNC counters 0:3 ++ */ ++ for (cnt = CNT0; cnt < CNTMAX; cnt++) { ++ if (flags & (1 << (cnt - CNT0))) { ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); ++ armv7_pmnc_reset_counter(cnt); ++ oprofile_add_sample(regs, cpu_cnt); ++ } ++ } ++ ++ /* ++ * Allow IRQ generation ++ */ ++ armv7_start_pmnc(); ++ ++ return IRQ_HANDLED; ++} ++ ++int armv7_request_interrupts(int *irqs, int nr) ++{ ++ unsigned int i; ++ int ret = 0; ++ ++ for (i = 0; i < nr; i++) { ++ ret = request_irq(irqs[i], armv7_pmnc_interrupt, ++ IRQF_DISABLED, "CP15 PMNC", NULL); ++ if (ret != 0) { ++ printk(KERN_ERR "oprofile: unable to request IRQ%u" ++ " for ARMv7\n", ++ irqs[i]); ++ break; ++ } ++ } ++ ++ if (i != nr) ++ while (i-- != 0) ++ free_irq(irqs[i], NULL); ++ ++ return ret; ++} ++ ++void armv7_release_interrupts(int *irqs, int nr) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr; i++) ++ free_irq(irqs[i], NULL); ++} ++ ++#ifdef DEBUG ++static void armv7_pmnc_dump_regs(void) ++{ ++ u32 val; ++ unsigned int cnt; ++ ++ printk(KERN_INFO "PMNC registers dump:\n"); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); ++ printk(KERN_INFO "PMNC =0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); ++ printk(KERN_INFO "CNTENS=0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); ++ printk(KERN_INFO "INTENS=0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); ++ printk(KERN_INFO "FLAGS =0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); ++ printk(KERN_INFO "SELECT=0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); ++ printk(KERN_INFO "CCNT =0x%08x\n", val); ++ ++ for (cnt = CNT0; cnt < CNTMAX; cnt++) { ++ armv7_pmnc_select_counter(cnt); ++ asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); ++ printk(KERN_INFO "CNT[%d] count =0x%08x\n", cnt-CNT0, val); ++ asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); ++ printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", cnt-CNT0, val); ++ } ++} ++#endif ++ ++ ++static int irqs[] = { ++#ifdef CONFIG_ARCH_OMAP3 ++ INT_34XX_BENCH_MPU_EMUL, ++#endif ++}; ++ ++static void armv7_pmnc_stop(void) ++{ ++#ifdef DEBUG ++ armv7_pmnc_dump_regs(); ++#endif ++ armv7_stop_pmnc(); ++ armv7_release_interrupts(irqs, ARRAY_SIZE(irqs)); ++} ++ ++static int armv7_pmnc_start(void) ++{ ++ int ret; ++ ++#ifdef DEBUG ++ armv7_pmnc_dump_regs(); ++#endif ++ ret = armv7_request_interrupts(irqs, ARRAY_SIZE(irqs)); ++ if (ret >= 0) ++ armv7_start_pmnc(); ++ ++ return ret; ++} ++ ++static int armv7_detect_pmnc(void) ++{ ++ return 0; ++} ++ ++struct op_arm_model_spec op_armv7_spec = { ++ .init = armv7_detect_pmnc, ++ .num_counters = 5, ++ .setup_ctrs = armv7_setup_pmnc, ++ .start = armv7_pmnc_start, ++ .stop = armv7_pmnc_stop, ++ .name = "arm/armv7", ++}; +diff --git a/arch/arm/oprofile/op_model_v7.h b/arch/arm/oprofile/op_model_v7.h +new file mode 100644 +index 0000000..08f40ea +--- /dev/null ++++ b/arch/arm/oprofile/op_model_v7.h +@@ -0,0 +1,101 @@ ++/** ++ * @file op_model_v7.h ++ * ARM v7 (Cortex A8) Event Monitor Driver ++ * ++ * @remark Copyright 2008 Jean Pihet <jpihet@mvista.com> ++ * @remark Copyright 2004 ARM SMP Development Team ++ * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com> ++ * @remark Copyright 2000-2004 MontaVista Software Inc ++ * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com> ++ * @remark Copyright 2004 Intel Corporation ++ * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk> ++ * @remark Copyright 2004 Oprofile Authors ++ * ++ * @remark Read the file COPYING ++ * ++ * @author Zwane Mwaikambo ++ */ ++#ifndef OP_MODEL_V7_H ++#define OP_MODEL_V7_H ++ ++/* ++ * Per-CPU PMNC: config reg ++ */ ++#define PMNC_E (1 << 0) /* Enable all counters */ ++#define PMNC_P (1 << 1) /* Reset all counters */ ++#define PMNC_C (1 << 2) /* Cycle counter reset */ ++#define PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ ++#define PMNC_X (1 << 4) /* Export to ETM */ ++#define PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ ++#define PMNC_MASK 0x3f /* Mask for writable bits */ ++ ++/* ++ * Available counters ++ */ ++#define CCNT 0 ++#define CNT0 1 ++#define CNT1 2 ++#define CNT2 3 ++#define CNT3 4 ++#define CNTMAX 5 ++ ++#define CPU_COUNTER(cpu, counter) ((cpu) * CNTMAX + (counter)) ++ ++/* ++ * CNTENS: counters enable reg ++ */ ++#define CNTENS_P0 (1 << 0) ++#define CNTENS_P1 (1 << 1) ++#define CNTENS_P2 (1 << 2) ++#define CNTENS_P3 (1 << 3) ++#define CNTENS_C (1 << 31) ++#define CNTENS_MASK 0x8000000f /* Mask for writable bits */ ++ ++/* ++ * CNTENC: counters disable reg ++ */ ++#define CNTENC_P0 (1 << 0) ++#define CNTENC_P1 (1 << 1) ++#define CNTENC_P2 (1 << 2) ++#define CNTENC_P3 (1 << 3) ++#define CNTENC_C (1 << 31) ++#define CNTENC_MASK 0x8000000f /* Mask for writable bits */ ++ ++/* ++ * INTENS: counters overflow interrupt enable reg ++ */ ++#define INTENS_P0 (1 << 0) ++#define INTENS_P1 (1 << 1) ++#define INTENS_P2 (1 << 2) ++#define INTENS_P3 (1 << 3) ++#define INTENS_C (1 << 31) ++#define INTENS_MASK 0x8000000f /* Mask for writable bits */ ++ ++/* ++ * EVTSEL: Event selection reg ++ */ ++#define EVTSEL_MASK 0x7f /* Mask for writable bits */ ++ ++/* ++ * SELECT: Counter selection reg ++ */ ++#define SELECT_MASK 0x1f /* Mask for writable bits */ ++ ++/* ++ * FLAG: counters overflow flag status reg ++ */ ++#define FLAG_P0 (1 << 0) ++#define FLAG_P1 (1 << 1) ++#define FLAG_P2 (1 << 2) ++#define FLAG_P3 (1 << 3) ++#define FLAG_C (1 << 31) ++#define FLAG_MASK 0x8000000f /* Mask for writable bits */ ++ ++ ++int armv7_setup_pmu(void); ++int armv7_start_pmu(void); ++int armv7_stop_pmu(void); ++int armv7_request_interrupts(int *, int); ++void armv7_release_interrupts(int *, int); ++ ++#endif +diff --git a/include/asm-arm/arch-omap/irqs.h +b/include/asm-arm/arch-omap/irqs.h +index c80e160..89ca90e 100644 +--- a/include/asm-arm/arch-omap/irqs.h ++++ b/include/asm-arm/arch-omap/irqs.h +@@ -297,6 +297,7 @@ + #define INT_243X_HS_USB_DMA 93 + #define INT_243X_CARKIT_IRQ 94 + ++#define INT_34XX_BENCH_MPU_EMUL 3 + #define INT_34XX_ST_MCBSP2_IRQ 4 + #define INT_34XX_ST_MCBSP3_IRQ 5 + #define INT_34XX_SYS_NIRQ 7 diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/read_die_ids.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/read_die_ids.patch new file mode 100644 index 0000000..3f6c930 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/read_die_ids.patch @@ -0,0 +1,23 @@ +OMAP2/3 TAP: enable debug messages + +From: Paul Walmsley <paul@pwsan.com> + +This patch causes the OMAP2/3 chip ID code to display the full DIE_ID registers at boot. + +--- + + arch/arm/mach-omap2/id.c | 1 + + 1 files changed, 1 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c +index c7f9ab7..a154b5e 100644 +--- a/arch/arm/mach-omap2/id.c ++++ b/arch/arm/mach-omap2/id.c +@@ -10,6 +10,7 @@ + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ ++#define DEBUG + + #include <linux/module.h> + #include <linux/kernel.h> diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/serialfix.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/serialfix.diff new file mode 100644 index 0000000..74c2eba --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/serialfix.diff @@ -0,0 +1,18 @@ +--- /tmp/pm34xx.c 2008-07-14 18:09:08.000000000 +0200 ++++ git/arch/arm/mach-omap2/pm34xx.c 2008-07-14 18:09:42.453198000 +0200 +@@ -398,13 +398,13 @@ + INT_34XX_PRCM_MPU_IRQ); + goto err1; + } +- ++/* + ret = pwrdm_for_each(pwrdms_setup); + if (ret) { + printk(KERN_ERR "Failed to setup powerdomains\n"); + goto err2; + } +- ++*/ + mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); + if (mpu_pwrdm == NULL) { + printk(KERN_ERR "Failed to get mpu_pwrdm\n"); diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/soc.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/soc.patch new file mode 100644 index 0000000..f4cce21 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/soc.patch @@ -0,0 +1,1154 @@ +diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig +index 3903ab7..468536d 100644 +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -44,3 +44,7 @@ config SND_SOC_CS4270_VD33_ERRATA + config SND_SOC_TLV320AIC3X + tristate + depends on SND_SOC && I2C ++ ++config SND_SOC_TWL4030 ++ tristate ++ depends on SND_SOC && I2C +diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile +index 4e1314c..d2c0b12 100644 +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -6,6 +6,7 @@ snd-soc-wm9712-objs := wm9712.o + snd-soc-wm9713-objs := wm9713.o + snd-soc-cs4270-objs := cs4270.o + snd-soc-tlv320aic3x-objs := tlv320aic3x.o ++snd-soc-twl4030-objs := twl4030.o + + obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o + obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o +@@ -15,3 +16,4 @@ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o + obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o + obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o + obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o ++obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o +diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c +new file mode 100644 +index 0000000..eb8370c +--- /dev/null ++++ b/sound/soc/codecs/twl4030.c +@@ -0,0 +1,625 @@ ++/* ++ * ALSA SoC TWL4030 codec driver ++ * ++ * Author: Steve Sakoman, <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/init.h> ++#include <linux/delay.h> ++#include <linux/pm.h> ++#include <linux/i2c.h> ++#include <linux/platform_device.h> ++#include <linux/i2c/twl4030.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/pcm_params.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++#include <sound/initval.h> ++ ++#include "twl4030.h" ++ ++/* ++ * twl4030 register cache & default register settings ++ */ ++static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { ++ 0x00, // this register not used ++ 0x93, // REG_CODEC_MODE (0x1) ++ 0xc3, // REG_OPTION (0x2) ++ 0x00, // REG_UNKNOWN (0x3) ++ 0x00, // REG_MICBIAS_CTL (0x4) ++ 0x34, // REG_ANAMICL (0x5) ++ 0x14, // REG_ANAMICR (0x6) ++ 0x0a, // REG_AVADC_CTL (0x7) ++ 0x00, // REG_ADCMICSEL (0x8) ++ 0x00, // REG_DIGMIXING (0x9) ++ 0x0c, // REG_ATXL1PGA (0xA) ++ 0x0c, // REG_ATXR1PGA (0xB) ++ 0x00, // REG_AVTXL2PGA (0xC) ++ 0x00, // REG_AVTXR2PGA (0xD) ++ 0x01, // REG_AUDIO_IF (0xE) ++ 0x00, // REG_VOICE_IF (0xF) ++ 0x00, // REG_ARXR1PGA (0x10) ++ 0x00, // REG_ARXL1PGA (0x11) ++ 0x6c, // REG_ARXR2PGA (0x12) ++ 0x6c, // REG_ARXL2PGA (0x13) ++ 0x00, // REG_VRXPGA (0x14) ++ 0x00, // REG_VSTPGA (0x15) ++ 0x00, // REG_VRX2ARXPGA (0x16) ++ 0x0c, // REG_AVDAC_CTL (0x17) ++ 0x00, // REG_ARX2VTXPGA (0x18) ++ 0x00, // REG_ARXL1_APGA_CTL (0x19) ++ 0x00, // REG_ARXR1_APGA_CTL (0x1A) ++ 0x4b, // REG_ARXL2_APGA_CTL (0x1B) ++ 0x4b, // REG_ARXR2_APGA_CTL (0x1C) ++ 0x00, // REG_ATX2ARXPGA (0x1D) ++ 0x00, // REG_BT_IF (0x1E) ++ 0x00, // REG_BTPGA (0x1F) ++ 0x00, // REG_BTSTPGA (0x20) ++ 0x00, // REG_EAR_CTL (0x21) ++ 0x24, // REG_HS_SEL (0x22) ++ 0x0a, // REG_HS_GAIN_SET (0x23) ++ 0x00, // REG_HS_POPN_SET (0x24) ++ 0x00, // REG_PREDL_CTL (0x25) ++ 0x00, // REG_PREDR_CTL (0x26) ++ 0x00, // REG_PRECKL_CTL (0x27) ++ 0x00, // REG_PRECKR_CTL (0x28) ++ 0x00, // REG_HFL_CTL (0x29) ++ 0x00, // REG_HFR_CTL (0x2A) ++ 0x00, // REG_ALC_CTL (0x2B) ++ 0x00, // REG_ALC_SET1 (0x2C) ++ 0x00, // REG_ALC_SET2 (0x2D) ++ 0x00, // REG_BOOST_CTL (0x2E) ++ 0x01, // REG_SOFTVOL_CTL (0x2F) ++ 0x00, // REG_DTMF_FREQSEL (0x30) ++ 0x00, // REG_DTMF_TONEXT1H (0x31) ++ 0x00, // REG_DTMF_TONEXT1L (0x32) ++ 0x00, // REG_DTMF_TONEXT2H (0x33) ++ 0x00, // REG_DTMF_TONEXT2L (0x34) ++ 0x00, // REG_DTMF_TONOFF (0x35) ++ 0x00, // REG_DTMF_WANONOFF (0x36) ++ 0x00, // REG_I2S_RX_SCRAMBLE_H (0x37) ++ 0x00, // REG_I2S_RX_SCRAMBLE_M (0x38) ++ 0x00, // REG_I2S_RX_SCRAMBLE_L (0x39) ++ 0x16, // REG_APLL_CTL (0x3A) ++ 0x00, // REG_DTMF_CTL (0x3B) ++ 0x00, // REG_DTMF_PGA_CTL2 (0x3C) ++ 0x00, // REG_DTMF_PGA_CTL1 (0x3D) ++ 0x00, // REG_MISC_SET_1 (0x3E) ++ 0x00, // REG_PCMBTMUX (0x3F) ++ 0x00, // REG_RX_PATH_SEL (0x43) ++ 0x00, // REG_VDL_APGA_CTL (0x44) ++ 0x00, // REG_VIBRA_CTL (0x45) ++ 0x00, // REG_VIBRA_SET (0x46) ++ 0x00, // REG_VIBRA_PWM_SET (0x47) ++ 0x00, // REG_ANAMIC_GAIN (0x48) ++ 0x00, // REG_MISC_SET_2 (0x49) ++}; ++ ++static void twl4030_dump_registers(void) ++{ ++ int i = 0; ++ u8 data; ++ ++ printk(KERN_INFO "TWL 4030 Register dump for Audio Module\n"); ++ ++ for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &data, i); ++ printk(KERN_INFO "Register[0x%02x]=0x%02x\n", i, data); ++ } ++} ++ ++struct twl4030_priv { ++ unsigned int dummy; ++}; ++ ++/* ++ * read twl4030 register cache ++ */ ++static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, ++ unsigned int reg) ++{ ++ u8 *cache = codec->reg_cache; ++ ++ return cache[reg]; ++} ++ ++/* ++ * write twl4030 register cache ++ */ ++static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, ++ u8 reg, u8 value) ++{ ++ u8 *cache = codec->reg_cache; ++ ++ if (reg >= TWL4030_CACHEREGNUM) ++ return; ++ cache[reg] = value; ++} ++ ++/* ++ * write to the twl4030 register space ++ */ ++static int twl4030_write(struct snd_soc_codec *codec, ++ unsigned int reg, unsigned int value) ++{ ++ twl4030_write_reg_cache(codec, reg, value); ++ return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); ++} ++ ++static void twl4030_init_chip(void) ++{ ++ unsigned char byte; ++ int i; ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_CODEC_MODE] & 0xfd, REG_CODEC_MODE); ++ ++ udelay(10); /* delay for power settling */ ++ ++ for (i = REG_OPTION; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, twl4030_reg[i], i); ++ } ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_CODEC_MODE], REG_CODEC_MODE); ++ ++ udelay(10); /* delay for power settling */ ++ ++ /* initiate offset cancellation */ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_ANAMICL] | 0x80, REG_ANAMICL); ++ ++ /* wait for offset cancellation to complete */ ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL); ++ while ((byte & 0x80) == 0x80) ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL); ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_MISC_SET_1] | 0x02, REG_MISC_SET_1); ++ ++} ++ ++static const struct snd_kcontrol_new twl4030_snd_controls[] = { ++ SOC_DOUBLE_R("Master Playback Volume", ++ REG_ARXL2PGA, REG_ARXR2PGA, ++ 0, 127, 0), ++ SOC_DOUBLE_R("Capture Volume", ++ REG_ATXL1PGA, REG_ATXR1PGA, ++ 0, 127, 0), ++}; ++ ++/* add non dapm controls */ ++static int twl4030_add_controls(struct snd_soc_codec *codec) ++{ ++ int err, i; ++ ++ for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) { ++ err = snd_ctl_add(codec->card, ++ snd_soc_cnew(&twl4030_snd_controls[i], ++ codec, NULL)); ++ if (err < 0) ++ return err; ++ } ++ ++ return 0; ++} ++ ++static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { ++ SND_SOC_DAPM_INPUT("INL"), ++ SND_SOC_DAPM_INPUT("INR"), ++ ++ SND_SOC_DAPM_OUTPUT("OUTL"), ++ SND_SOC_DAPM_OUTPUT("OUTR"), ++ ++ SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), ++ SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), ++ ++ SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0), ++ SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0), ++}; ++ ++static const char *intercon[][3] = { ++ /* outputs */ ++ {"OUTL", NULL, "DACL"}, ++ {"OUTR", NULL, "DACR"}, ++ ++ /* inputs */ ++ {"ADCL", NULL, "INL"}, ++ {"ADCR", NULL, "INR"}, ++ ++ /* terminator */ ++ {NULL, NULL, NULL}, ++}; ++ ++static int twl4030_add_widgets(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++) ++ snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]); ++ ++ /* set up audio path interconnects */ ++ for (i = 0; intercon[i][0] != NULL; i++) ++ snd_soc_dapm_connect_input(codec, intercon[i][0], ++ intercon[i][1], intercon[i][2]); ++ ++ snd_soc_dapm_new_widgets(codec); ++ return 0; ++} ++ ++static int twl4030_dapm_event(struct snd_soc_codec *codec, int event) ++{ ++ ++ printk(KERN_INFO "TWL4030 Audio Codec dapm event\n"); ++ switch (event) { ++ case SNDRV_CTL_POWER_D0: /* full On */ ++ break; ++ case SNDRV_CTL_POWER_D1: /* partial On */ ++ case SNDRV_CTL_POWER_D2: /* partial On */ ++ break; ++ case SNDRV_CTL_POWER_D3hot: /* off, with power */ ++ break; ++ case SNDRV_CTL_POWER_D3cold: /* off, without power */ ++ break; ++ } ++ codec->dapm_state = event; ++ ++ return 0; ++} ++ ++static void twl4030_power_up (struct snd_soc_codec *codec, u8 mode) ++{ ++ u8 popn, hsgain; ++ ++ twl4030_write(codec, REG_CODEC_MODE, mode & ~CODECPDZ); ++ twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ); ++ udelay(10); ++ ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); ++ popn &= RAMP_DELAY; ++ popn |= VMID_EN | RAMP_DELAY_161MS; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ hsgain = HSR_GAIN_0DB| HSL_GAIN_0DB; ++ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); ++ ++ popn |= RAMP_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++} ++ ++static void twl4030_power_down (struct snd_soc_codec *codec) ++{ ++ u8 popn, hsgain, mode; ++ ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); ++ popn &= ~RAMP_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ hsgain = HSR_GAIN_PWR_DOWN | HSL_GAIN_PWR_DOWN; ++ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); ++ ++ popn &= ~VMID_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ udelay(10); ++} ++ ++ ++static int twl4030_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_device *socdev = rtd->socdev; ++ struct snd_soc_codec *codec = socdev->codec; ++ struct twl4030_priv *twl4030 = codec->private_data; ++ u8 mode, old_mode, format, old_format; ++ ++ ++ /* bit rate */ ++ old_mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ; ++ mode = old_mode; ++ mode &= ~APLL_RATE; ++ switch (params_rate(params)) { ++ case 44100: ++ mode |= APLL_RATE_44100; ++ break; ++ case 48000: ++ mode |= APLL_RATE_48000; ++ break; ++ default: ++ printk(KERN_INFO "TWL4030 hw params: unknown rate %d\n", params_rate(params)); ++ return -EINVAL; ++ } ++ ++ if (mode != old_mode) { ++ /* change rate and turn codec back on */ ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ ++ /* sample size */ ++ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ format = old_format; ++ format &= ~DATA_WIDTH; ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ format |= DATA_WIDTH_16S_16W; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ format |= DATA_WIDTH_32S_24W; ++ break; ++ default: ++ printk(KERN_INFO "TWL4030 hw params: unknown format %d\n", params_format(params)); ++ return -EINVAL; ++ } ++ ++ if (format != old_format) { ++ ++ /* turn off codec before changing format */ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ ++ /* change format */ ++ twl4030_write(codec, REG_AUDIO_IF, format); ++ ++ /* turn on codec */ ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ return 0; ++} ++ ++static int twl4030_mute(struct snd_soc_codec_dai *dai, int mute) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ ++ u8 ldac_reg = twl4030_read_reg_cache(codec, REG_ARXL2PGA); ++ u8 rdac_reg = twl4030_read_reg_cache(codec, REG_ARXR2PGA); ++ ++ if (mute) { ++ /* printk(KERN_INFO "TWL4030 Audio Codec mute\n"); */ ++ twl4030_write(codec, REG_ARXL2PGA, 0x00); ++ twl4030_write(codec, REG_ARXR2PGA, 0x00); ++ twl4030_write_reg_cache(codec, REG_ARXL2PGA, ldac_reg); ++ twl4030_write_reg_cache(codec, REG_ARXR2PGA, rdac_reg); ++ } ++ else { ++ /* printk(KERN_INFO "TWL4030 Audio Codec unmute: %02x/%02x\n", ldac_reg, rdac_reg); */ ++ twl4030_write(codec, REG_ARXL2PGA, ldac_reg); ++ twl4030_write(codec, REG_ARXR2PGA, rdac_reg); ++ } ++ ++ return 0; ++} ++ ++static int twl4030_set_dai_fmt(struct snd_soc_codec_dai *codec_dai, ++ unsigned int fmt) ++{ ++ struct snd_soc_codec *codec = codec_dai->codec; ++ struct twl4030_priv *twl4030 = codec->private_data; ++ u8 mode, old_format, format; ++ ++ /* get format */ ++ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ format = old_format; ++ ++ /* set master/slave audio interface */ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++ /* printk(KERN_INFO "TWL4030 set dai fmt: master\n"); */ ++ format &= ~(AIF_SLAVE_EN); ++ format |= CLK256FS_EN; ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ /* printk(KERN_INFO "TWL4030 set dai fmt: slave\n"); */ ++ format &= ~(CLK256FS_EN); ++ format |= AIF_SLAVE_EN; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* interface format */ ++ format &= ~AIF_FORMAT; ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ /* printk(KERN_INFO "TWL4030 set dai fmt: i2s\n"); */ ++ format |= AIF_FORMAT_CODEC; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (format != old_format) { ++ ++ /* turn off codec before changing format */ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ ++ /* change format */ ++ twl4030_write(codec, REG_AUDIO_IF, format); ++ ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ ++ return 0; ++} ++ ++#define TWL4030_RATES SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 ++#define TWL4030_FORMATS SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE ++ ++struct snd_soc_codec_dai twl4030_dai = { ++ .name = "twl4030", ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = TWL4030_RATES, ++ .formats = TWL4030_FORMATS,}, ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = TWL4030_RATES, ++ .formats = TWL4030_FORMATS,}, ++ .ops = { ++ .hw_params = twl4030_hw_params, ++ }, ++ .dai_ops = { ++ .digital_mute = twl4030_mute, ++ .set_fmt = twl4030_set_dai_fmt, ++ } ++}; ++ ++EXPORT_SYMBOL_GPL(twl4030_dai); ++ ++static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec suspend\n"); ++ twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3cold); ++ ++ return 0; ++} ++ ++static int twl4030_resume(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ int i; ++ u16 *cache = codec->reg_cache; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec resume\n"); ++ /* Sync reg_cache with the hardware */ ++ for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, cache[i], i); ++ } ++ twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3hot); ++ twl4030_dapm_event(codec, codec->suspend_dapm_state); ++ return 0; ++} ++ ++/* ++ * initialize the driver ++ * register the mixer and dsp interfaces with the kernel ++ */ ++ ++static int twl4030_init(struct snd_soc_device *socdev) ++{ ++ struct snd_soc_codec *codec = socdev->codec; ++ int ret = 0; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec init \n"); ++ ++ codec->name = "twl4030"; ++ codec->owner = THIS_MODULE; ++ codec->read = twl4030_read_reg_cache; ++ codec->write = twl4030_write; ++ codec->dapm_event = twl4030_dapm_event; ++ codec->dai = &twl4030_dai; ++ codec->num_dai = 1; ++ codec->reg_cache_size = sizeof(twl4030_reg); ++ codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), GFP_KERNEL); ++ if (codec->reg_cache == NULL) ++ return -ENOMEM; ++ ++ /* register pcms */ ++ ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); ++ if (ret < 0) { ++ printk(KERN_ERR "twl4030: failed to create pcms\n"); ++ goto pcm_err; ++ } ++ ++ twl4030_add_controls(codec); ++ twl4030_add_widgets(codec); ++ ++ ret = snd_soc_register_card(socdev); ++ if (ret < 0) { ++ printk(KERN_ERR "twl4030: failed to register card\n"); ++ goto card_err; ++ } ++ ++ twl4030_init_chip(); ++ twl4030_power_up(codec, APLL_RATE_44100 | OPT_MODE); ++ ++ return ret; ++ ++card_err: ++ printk(KERN_INFO "TWL4030 Audio Codec init card error\n"); ++ snd_soc_free_pcms(socdev); ++ snd_soc_dapm_free(socdev); ++pcm_err: ++ printk(KERN_INFO "TWL4030 Audio Codec init pcm error\n"); ++ kfree(codec->reg_cache); ++ return ret; ++} ++ ++static struct snd_soc_device *twl4030_socdev; ++ ++static int twl4030_probe(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec; ++ struct twl4030_priv *twl4030; ++ ++ codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); ++ if (codec == NULL) ++ return -ENOMEM; ++ ++ twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL); ++ if (twl4030 == NULL) { ++ kfree(codec); ++ return -ENOMEM; ++ } ++ ++ codec->private_data = twl4030; ++ socdev->codec = codec; ++ mutex_init(&codec->mutex); ++ INIT_LIST_HEAD(&codec->dapm_widgets); ++ INIT_LIST_HEAD(&codec->dapm_paths); ++ ++ twl4030_socdev = socdev; ++ twl4030_init(socdev); ++ ++ return 0; ++} ++ ++static int twl4030_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec remove\n"); ++ kfree(codec->private_data); ++ kfree(codec); ++ ++ return 0; ++} ++ ++struct snd_soc_codec_device soc_codec_dev_twl4030 = { ++ .probe = twl4030_probe, ++ .remove = twl4030_remove, ++ .suspend = twl4030_suspend, ++ .resume = twl4030_resume, ++}; ++EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); ++ ++MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); ++MODULE_AUTHOR("Steve Sakoman"); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h +new file mode 100644 +index 0000000..e126f96 +--- /dev/null ++++ b/sound/soc/codecs/twl4030.h +@@ -0,0 +1,152 @@ ++/* ++ * ALSA SoC TWL4030 codec driver ++ * ++ * Author: Steve Sakoman, <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __TWL4030_AUDIO_H__ ++#define __TWL4030_AUDIO_H__ ++ ++#define REG_CODEC_MODE 0x1 ++#define REG_OPTION 0x2 ++#define REG_UNKNOWN 0x3 ++#define REG_MICBIAS_CTL 0x4 ++#define REG_ANAMICL 0x5 ++#define REG_ANAMICR 0x6 ++#define REG_AVADC_CTL 0x7 ++#define REG_ADCMICSEL 0x8 ++#define REG_DIGMIXING 0x9 ++#define REG_ATXL1PGA 0xA ++#define REG_ATXR1PGA 0xB ++#define REG_AVTXL2PGA 0xC ++#define REG_AVTXR2PGA 0xD ++#define REG_AUDIO_IF 0xE ++#define REG_VOICE_IF 0xF ++#define REG_ARXR1PGA 0x10 ++#define REG_ARXL1PGA 0x11 ++#define REG_ARXR2PGA 0x12 ++#define REG_ARXL2PGA 0x13 ++#define REG_VRXPGA 0x14 ++#define REG_VSTPGA 0x15 ++#define REG_VRX2ARXPGA 0x16 ++#define REG_AVDAC_CTL 0x17 ++#define REG_ARX2VTXPGA 0x18 ++#define REG_ARXL1_APGA_CTL 0x19 ++#define REG_ARXR1_APGA_CTL 0x1A ++#define REG_ARXL2_APGA_CTL 0x1B ++#define REG_ARXR2_APGA_CTL 0x1C ++#define REG_ATX2ARXPGA 0x1D ++#define REG_BT_IF 0x1E ++#define REG_BTPGA 0x1F ++#define REG_BTSTPGA 0x20 ++#define REG_EAR_CTL 0x21 ++#define REG_HS_SEL 0x22 ++#define REG_HS_GAIN_SET 0x23 ++#define REG_HS_POPN_SET 0x24 ++#define REG_PREDL_CTL 0x25 ++#define REG_PREDR_CTL 0x26 ++#define REG_PRECKL_CTL 0x27 ++#define REG_PRECKR_CTL 0x28 ++#define REG_HFL_CTL 0x29 ++#define REG_HFR_CTL 0x2A ++#define REG_ALC_CTL 0x2B ++#define REG_ALC_SET1 0x2C ++#define REG_ALC_SET2 0x2D ++#define REG_BOOST_CTL 0x2E ++#define REG_SOFTVOL_CTL 0x2F ++#define REG_DTMF_FREQSEL 0x30 ++#define REG_DTMF_TONEXT1H 0x31 ++#define REG_DTMF_TONEXT1L 0x32 ++#define REG_DTMF_TONEXT2H 0x33 ++#define REG_DTMF_TONEXT2L 0x34 ++#define REG_DTMF_TONOFF 0x35 ++#define REG_DTMF_WANONOFF 0x36 ++#define REG_I2S_RX_SCRAMBLE_H 0x37 ++#define REG_I2S_RX_SCRAMBLE_M 0x38 ++#define REG_I2S_RX_SCRAMBLE_L 0x39 ++#define REG_APLL_CTL 0x3A ++#define REG_DTMF_CTL 0x3B ++#define REG_DTMF_PGA_CTL2 0x3C ++#define REG_DTMF_PGA_CTL1 0x3D ++#define REG_MISC_SET_1 0x3E ++#define REG_PCMBTMUX 0x3F ++#define REG_RX_PATH_SEL 0x43 ++#define REG_VDL_APGA_CTL 0x44 ++#define REG_VIBRA_CTL 0x45 ++#define REG_VIBRA_SET 0x46 ++#define REG_VIBRA_PWM_SET 0x47 ++#define REG_ANAMIC_GAIN 0x48 ++#define REG_MISC_SET_2 0x49 ++ ++#define TWL4030_CACHEREGNUM REG_MISC_SET_2 + 1 ++ ++/* Bitfield Definitions */ ++ ++/* CODEC_MODE (0x01) Fields */ ++ ++#define APLL_RATE 0xF0 ++#define APLL_RATE_8000 0x00 ++#define APLL_RATE_11025 0x10 ++#define APLL_RATE_12000 0x20 ++#define APLL_RATE_16000 0x40 ++#define APLL_RATE_22050 0x50 ++#define APLL_RATE_24000 0x60 ++#define APLL_RATE_32000 0x80 ++#define APLL_RATE_44100 0x90 ++#define APLL_RATE_48000 0xa0 ++#define SEL_16K 0x04 ++#define CODECPDZ 0x02 ++#define OPT_MODE 0x01 ++ ++/* AUDIO_IF (0x0E) Fields */ ++ ++#define AIF_SLAVE_EN 0x80 ++#define DATA_WIDTH 0x60 ++#define DATA_WIDTH_16S_16W 0x00 ++#define DATA_WIDTH_32S_16W 0x40 ++#define DATA_WIDTH_32S_24W 0x60 ++#define AIF_FORMAT 0x18 ++#define AIF_FORMAT_CODEC 0x00 ++#define AIF_FORMAT_LEFT 0x08 ++#define AIF_FORMAT_RIGHT 0x10 ++#define AIF_FORMAT_TDM 0x18 ++#define AIF_TRI_EN 0x04 ++#define CLK256FS_EN 0x02 ++#define AIF_EN 0x01 ++ ++/* HS_GAIN_SET (0x23) Fields */ ++ ++#define HSR_GAIN 0x0c ++#define HSR_GAIN_PWR_DOWN 0x00 ++#define HSR_GAIN_PLUS_6DB 0x04 ++#define HSR_GAIN_0DB 0x08 ++#define HSR_GAIN_MINUS_6DB 0x0c ++#define HSL_GAIN 0x0c ++#define HSL_GAIN_PWR_DOWN 0x00 ++#define HSL_GAIN_PLUS_6DB 0x01 ++#define HSL_GAIN_0DB 0x02 ++#define HSL_GAIN_MINUS_6DB 0x03 ++ ++/* HS_POPN_SET (0x24) Fields */ ++ ++#define VMID_EN 0x40 ++#define EXTMUTE 0x20 ++#define RAMP_DELAY 0x1C ++#define RAMP_DELAY_20MS 0x00 ++#define RAMP_DELAY_40MS 0x04 ++#define RAMP_DELAY_81MS 0x08 ++#define RAMP_DELAY_161MS 0x0c ++#define RAMP_DELAY_323MS 0x10 ++#define RAMP_DELAY_645MS 0x14 ++#define RAMP_DELAY_1291MS 0x18 ++#define RAMP_DELAY_2581MS 0x1c ++#define RAMP_EN 0x02 ++ ++extern struct snd_soc_codec_dai twl4030_dai; ++extern struct snd_soc_codec_device soc_codec_dev_twl4030; ++ ++#endif /* End of __TWL4030_AUDIO_H__ */ +diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig +index 0230d83..8703cea 100644 +--- a/sound/soc/omap/Kconfig ++++ b/sound/soc/omap/Kconfig +@@ -16,4 +16,20 @@ config SND_OMAP_SOC_N810 + help + Say Y if you want to add support for SoC audio on Nokia N810. + ++config SND_OMAP_SOC_OMAP3EVM ++ tristate "SoC Audio support for OMAP3 EVM" ++ depends on SND_OMAP_SOC && MACH_OMAP3EVM ++ select SND_OMAP_SOC_MCBSP ++ select SND_SOC_TWL4030 ++ help ++ Say Y if you want to add support for SoC audio on the OMAP3 EVM. ++ ++config SND_OMAP_SOC_OMAP3BEAGLE ++ tristate "SoC Audio support for OMAP3 Beagle" ++ depends on SND_OMAP_SOC && MACH_OMAP3_BEAGLE ++ select SND_OMAP_SOC_MCBSP ++ select SND_SOC_TWL4030 ++ help ++ Say Y if you want to add support for SoC audio on the OMAP3 Beagle. ++ + endmenu +diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile +index d8d8d58..638a240 100644 +--- a/sound/soc/omap/Makefile ++++ b/sound/soc/omap/Makefile +@@ -7,5 +7,10 @@ obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o + + # OMAP Machine Support + snd-soc-n810-objs := n810.o ++snd-soc-omap3evm-objs := omap3evm.o ++snd-soc-omap3beagle-objs := omap3beagle.o + + obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o ++obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o ++obj-$(CONFIG_SND_OMAP_SOC_OMAP3BEAGLE) += snd-soc-omap3beagle.o ++ +diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c +new file mode 100644 +index 0000000..878f894 +--- /dev/null ++++ b/sound/soc/omap/omap3beagle.c +@@ -0,0 +1,142 @@ ++/* ++ * omap3beagle.c -- SoC audio for OMAP3 Beagle ++ * ++ * Author: Steve Sakoman <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include <linux/clk.h> ++#include <linux/platform_device.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++ ++#include <asm/mach-types.h> ++#include <asm/arch/hardware.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/mcbsp.h> ++ ++#include "omap-mcbsp.h" ++#include "omap-pcm.h" ++#include "../codecs/twl4030.h" ++ ++static int omap3beagle_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; ++ int ret; ++ ++ /* Set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set codec DAI configuration\n"); ++ return ret; ++ } ++ ++ /* Set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set cpu DAI configuration\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops omap3beagle_ops = { ++ .hw_params = omap3beagle_hw_params, ++}; ++ ++/* Digital audio interface glue - connects codec <--> CPU */ ++static struct snd_soc_dai_link omap3beagle_dai = { ++ .name = "TWL4030", ++ .stream_name = "TWL4030", ++ .cpu_dai = &omap_mcbsp_dai[0], ++ .codec_dai = &twl4030_dai, ++ .ops = &omap3beagle_ops, ++}; ++ ++/* Audio machine driver */ ++static struct snd_soc_machine snd_soc_machine_omap3beagle = { ++ .name = "omap3beagle", ++ .dai_link = &omap3beagle_dai, ++ .num_links = 1, ++}; ++ ++/* Audio subsystem */ ++static struct snd_soc_device omap3beagle_snd_devdata = { ++ .machine = &snd_soc_machine_omap3beagle, ++ .platform = &omap_soc_platform, ++ .codec_dev = &soc_codec_dev_twl4030, ++}; ++ ++static struct platform_device *omap3beagle_snd_device; ++ ++static int __init omap3beagle_soc_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "OMAP3 Beagle SoC init\n"); ++ if (!machine_is_omap3_beagle()) { ++ printk(KERN_INFO "Not OMAP3 Beagle!\n"); ++ return -ENODEV; ++ } ++ ++ omap3beagle_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!omap3beagle_snd_device) { ++ printk(KERN_INFO "Platform device allocation failed\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(omap3beagle_snd_device, &omap3beagle_snd_devdata); ++ omap3beagle_snd_devdata.dev = &omap3beagle_snd_device->dev; ++ *(unsigned int *)omap3beagle_dai.cpu_dai->private_data = 1; /* McBSP2 */ ++ ++ ret = platform_device_add(omap3beagle_snd_device); ++ if (ret) ++ goto err1; ++ ++ return 0; ++ ++err1: ++ printk(KERN_INFO "Unable to add platform device\n"); ++ platform_device_put(omap3beagle_snd_device); ++ ++ return ret; ++} ++ ++static void __exit omap3beagle_soc_exit(void) ++{ ++ printk(KERN_INFO "OMAP3 Beagle SoC exit\n"); ++ platform_device_unregister(omap3beagle_snd_device); ++} ++ ++module_init(omap3beagle_soc_init); ++module_exit(omap3beagle_soc_exit); ++ ++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>"); ++MODULE_DESCRIPTION("ALSA SoC OMAP3 Beagle"); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c +new file mode 100644 +index 0000000..a64c788 +--- /dev/null ++++ b/sound/soc/omap/omap3evm.c +@@ -0,0 +1,142 @@ ++/* ++ * omap3evm.c -- SoC audio for OMAP3 EVM ++ * ++ * Author: Steve Sakoman <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include <linux/clk.h> ++#include <linux/platform_device.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++ ++#include <asm/mach-types.h> ++#include <asm/arch/hardware.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/mcbsp.h> ++ ++#include "omap-mcbsp.h" ++#include "omap-pcm.h" ++#include "../codecs/twl4030.h" ++ ++static int omap3evm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; ++ int ret; ++ ++ /* Set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set codec DAI configuration\n"); ++ return ret; ++ } ++ ++ /* Set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set cpu DAI configuration\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops omap3evm_ops = { ++ .hw_params = omap3evm_hw_params, ++}; ++ ++/* Digital audio interface glue - connects codec <--> CPU */ ++static struct snd_soc_dai_link omap3evm_dai = { ++ .name = "TWL4030", ++ .stream_name = "TWL4030", ++ .cpu_dai = &omap_mcbsp_dai[0], ++ .codec_dai = &twl4030_dai, ++ .ops = &omap3evm_ops, ++}; ++ ++/* Audio machine driver */ ++static struct snd_soc_machine snd_soc_machine_omap3evm = { ++ .name = "omap3evm", ++ .dai_link = &omap3evm_dai, ++ .num_links = 1, ++}; ++ ++/* Audio subsystem */ ++static struct snd_soc_device omap3evm_snd_devdata = { ++ .machine = &snd_soc_machine_omap3evm, ++ .platform = &omap_soc_platform, ++ .codec_dev = &soc_codec_dev_twl4030, ++}; ++ ++static struct platform_device *omap3evm_snd_device; ++ ++static int __init omap3evm_soc_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "OMAP3 EVM SoC init\n"); ++ if (!machine_is_omap3evm()) { ++ printk(KERN_INFO "Not OMAP3 EVM!\n"); ++ return -ENODEV; ++ } ++ ++ omap3evm_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!omap3evm_snd_device) { ++ printk(KERN_INFO "Platform device allocation failed\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(omap3evm_snd_device, &omap3evm_snd_devdata); ++ omap3evm_snd_devdata.dev = &omap3evm_snd_device->dev; ++ *(unsigned int *)omap3evm_dai.cpu_dai->private_data = 1; /* McBSP2 */ ++ ++ ret = platform_device_add(omap3evm_snd_device); ++ if (ret) ++ goto err1; ++ ++ return 0; ++ ++err1: ++ printk(KERN_INFO "Unable to add platform device\n"); ++ platform_device_put(omap3evm_snd_device); ++ ++ return ret; ++} ++ ++static void __exit omap3evm_soc_exit(void) ++{ ++ printk(KERN_INFO "OMAP3 EVM SoC exit\n"); ++ platform_device_unregister(omap3evm_snd_device); ++} ++ ++module_init(omap3evm_soc_init); ++module_exit(omap3evm_soc_exit); ++ ++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>"); ++MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM"); ++MODULE_LICENSE("GPL"); diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/timer-suppression.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/timer-suppression.patch new file mode 100644 index 0000000..04362c9 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/timer-suppression.patch @@ -0,0 +1,43 @@ +diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c +index b854a89..26f5569 100644 +--- a/kernel/time/tick-sched.c ++++ b/kernel/time/tick-sched.c +@@ -253,6 +253,16 @@ void tick_nohz_stop_sched_tick(void) + + /* Schedule the tick, if we are at least one jiffie off */ + if ((long)delta_jiffies >= 1) { ++ /* ++ * calculate the expiry time for the next timer wheel ++ * timer ++ */ ++ expires = ktime_add_ns(last_update, tick_period.tv64 * ++ delta_jiffies); ++ ++ /* Skip reprogram of event if its not changed */ ++ if(ts->tick_stopped && ktime_equal(expires, dev->next_event)) ++ goto out2; + + if (delta_jiffies > 1) + cpu_set(cpu, nohz_cpu_mask); +@@ -304,12 +314,7 @@ void tick_nohz_stop_sched_tick(void) + goto out; + } + +- /* +- * calculate the expiry time for the next timer wheel +- * timer +- */ +- expires = ktime_add_ns(last_update, tick_period.tv64 * +- delta_jiffies); ++ /* Mark expiries */ + ts->idle_expires = expires; + + if (ts->nohz_mode == NOHZ_MODE_HIGHRES) { +@@ -328,6 +333,7 @@ void tick_nohz_stop_sched_tick(void) + tick_do_update_jiffies64(ktime_get()); + cpu_clear(cpu, nohz_cpu_mask); + } ++out2: + raise_softirq_irqoff(TIMER_SOFTIRQ); + out: + ts->next_jiffies = next_jiffies; |
