path: root/meta-aspeed/recipes-bsp/u-boot/files/patch-2013.07/0002-Create-snapshot-of-OpenBMC.patch

From 19459c799ac0a521082d6d79e68ffc3decb18ea2 Mon Sep 17 00:00:00 2001
From: Ori Bernstein <orib@fb.com>
Date: Thu, 3 Sep 2015 11:28:27 -0700
Subject: [PATCH] Create snapshot of OpenBMC

---
 .../u-boot-v2013.07/board/aspeed/ast2400/ast2400.c |  20 +-
 .../board/aspeed/ast2400/platform.S                |  35 ++
 .../u-boot/files/u-boot-v2013.07/boards.cfg        |   3 +
 .../files/u-boot-v2013.07/drivers/net/aspeednic.c  |   3 +-
 .../u-boot-v2013.07/include/configs/ast2400.h      |   1 +
 .../u-boot-v2013.07/include/configs/fbplatform1.h  | 353 ++++++++++++++++++++
 .../u-boot-v2013.07/include/configs/fbyosemite.h   | 353 ++++++++++++++++++++
 .../u-boot-v2013.07/include/configs/wedge100.h     | 354 +++++++++++++++++++++
 8 files changed, 1117 insertions(+), 5 deletions(-)
 create mode 100644 meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/fbplatform1.h
 create mode 100644 meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/fbyosemite.h
 create mode 100644 meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/wedge100.h

diff --git a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/board/aspeed/ast2400/ast2400.c b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/board/aspeed/ast2400/ast2400.c
index 55ed6b7..125957e 100644
--- a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/board/aspeed/ast2400/ast2400.c
+++ b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/board/aspeed/ast2400/ast2400.c
@@ -194,15 +194,27 @@ int ast1070_calibration()
 static void watchdog_init()
 {
 #ifdef CONFIG_ASPEED_ENABLE_WATCHDOG
-#define AST_WDT_BASE 0x1e785000
+#define AST_WDT1_BASE 0x1e785000
+#define AST_WDT2_BASE 0x1e785020
 #define AST_WDT_CLK (1*1000*1000) /* 1M clock source */
   u32 reload = AST_WDT_CLK * CONFIG_ASPEED_WATCHDOG_TIMEOUT;
+#ifdef CONFIG_ASPEED_ENABLE_DUAL_BOOT_WATCHDOG
+  /* dual boot watchdog is enabled */
   /* set the reload value */
-  __raw_writel(reload, AST_WDT_BASE + 0x04);
+  reload = AST_WDT_CLK * CONFIG_ASPEED_WATCHDOG_DUAL_BOOT_TIMEOUT;
+  /* set the reload value */
+  __raw_writel(reload, AST_WDT2_BASE + 0x04);
+  /* magic word to reload */
+  __raw_writel(0x4755, AST_WDT2_BASE + 0x08);
+  printf("Dual boot watchdog: %us\n", CONFIG_ASPEED_WATCHDOG_DUAL_BOOT_TIMEOUT);
+#endif
+  reload = AST_WDT_CLK * CONFIG_ASPEED_WATCHDOG_TIMEOUT;
+  /* set the reload value */
+  __raw_writel(reload, AST_WDT1_BASE + 0x04);
   /* magic word to reload */
-  __raw_writel(0x4755, AST_WDT_BASE + 0x08);
+  __raw_writel(0x4755, AST_WDT1_BASE + 0x08);
   /* start the watchdog with 1M clk src and reset whole chip */
-  __raw_writel(0x33, AST_WDT_BASE + 0x0c);
+  __raw_writel(0x33, AST_WDT1_BASE + 0x0c);
   printf("Watchdog: %us\n", CONFIG_ASPEED_WATCHDOG_TIMEOUT);
 #endif
 }
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/board/aspeed/ast2400/platform.S b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/board/aspeed/ast2400/platform.S
index dd94da0..64967f4 100644
--- a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/board/aspeed/ast2400/platform.S
+++ b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/board/aspeed/ast2400/platform.S
@@ -333,10 +333,45 @@ set_MPLL:
     and r1, r2, r1
     str r1, [r0]
 
+/* Yosemite Platform specific Initialization */
+#ifdef CONFIG_YOSEMITE
+/*
+ * Disable WDT2 before the 2nd SPI flash is tried
+ * TODO: Need to detect booting from 2nd flash and recover
+ */
+    ldr r0, =0x1e78502c
+    mov r1, #0x0
+    str r1, [r0]
+
+/* Use GPIOE2/GPIOE3 to select BMC Output on debug console */
+    ldr r1, =0x0C
+    ldr r0, =0x1e780024
+    str r1, [r0]
+
+    ldr r0, =0x1e780020
+    str r1, [r0]
+
+    ldr r1, = 0x80
+    ldr r0, =0x1e780084
+    str r1, [r0]
+
+
+    ldr r1, = 0x80
+    ldr r0, =0x1e780080
+    str r1, [r0]
+
+    ldr r1, = 0x0
+    ldr r0, =0x1e780080
+    str r1, [r0]
+#endif
+
 /* Debug - UART console message */
+// Enable UART3/4 only for non-yosemite platform
+#ifndef CONFIG_YOSEMITE
     ldr r0, =0x1e6e2080
     ldr r1, =0xFFFF0000                          @ enable UART3 and UART4
     str r1, [r0]
+#endif
 
     ldr r0, =CONFIG_ASPEED_COM_LCR
     mov r1, #0x83
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/boards.cfg b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/boards.cfg
index ce6bff1..556de75 100644
--- a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/boards.cfg
+++ b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/boards.cfg
@@ -73,6 +73,9 @@ VCMA9                        arm         arm920t     vcma9               mpl
 smdk2410                     arm         arm920t     -                   samsung        s3c24x0
 omap1510inn                  arm         arm925t     -                   ti
 wedge                        arm         arm926ejs   ast2400             aspeed         aspeed
+wedge100                     arm         arm926ejs   ast2400             aspeed         aspeed
+fbyosemite                   arm         arm926ejs   ast2400             aspeed         aspeed
+fbplatform1                  arm         arm926ejs   ast2400             aspeed         aspeed
 integratorap_cm926ejs        arm         arm926ejs   integrator          armltd         -           integratorap:CM926EJ_S
 integratorcp_cm926ejs        arm         arm926ejs   integrator          armltd         -           integratorcp:CM924EJ_S
 aspenite                     arm         arm926ejs   -                   Marvell        armada100
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/drivers/net/aspeednic.c b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/drivers/net/aspeednic.c
index d75ef67..86f6dec 100644
--- a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/drivers/net/aspeednic.c
+++ b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/drivers/net/aspeednic.c
@@ -471,8 +471,8 @@ int aspeednic_initialize(bd_t *bis)
   struct eth_device*  dev;
 
 #if defined(CONFIG_AST2300_FPGA_2) || defined(CONFIG_AST2300) || defined(CONFIG_AST3100) || defined(CONFIG_AST2400)
-//AST2300
 //MAC1 CLOCK/RESET/PHY_LINK/MDC_MDIO in SCU
+#ifdef CONFIG_MAC1_ENABLE
   SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL));
   *(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL) = cpu_to_le32(SCURegister | 0x800);
   udelay(100);
@@ -494,6 +494,7 @@ int aspeednic_initialize(bd_t *bis)
   SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL1_REG));
   *(volatile u_long *)(SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL1_REG) = cpu_to_le32(SCURegister | (MAC1_PHY_LINK));
 #endif
+#endif
 
 //MAC2 CLOCK/RESET/PHY_LINK/MDC_MDIO
 #ifdef CONFIG_MAC2_ENABLE
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/ast2400.h b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/ast2400.h
index 670fcfd..4c43d6f 100644
--- a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/ast2400.h
+++ b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/ast2400.h
@@ -284,6 +284,7 @@
 #define __LITTLE_ENDIAN_BITFIELD
 #define CONFIG_MAC_PARTITION
 #define CONFIG_ASPEEDNIC
+#define CONFIG_MAC1_ENABLE
 #define CONFIG_MAC1_PHY_LINK_INTERRUPT
 #define CONFIG_MAC2_ENABLE
 #define CONFIG_MAC2_PHY_LINK_INTERRUPT
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/fbplatform1.h b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/fbplatform1.h
new file mode 100644
index 0000000..22718fb
--- /dev/null
+++ b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/fbplatform1.h
@@ -0,0 +1,353 @@
+/*
+ * Copyright 2015-present Facebook. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Uncommit the following line to enable JTAG in u-boot */
+//#define CONFIG_ASPEED_ENABLE_JTAG
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+//#define CONFIG_INIT_CRITICAL			/* define for U-BOOT 1.1.1 */
+#undef  CONFIG_INIT_CRITICAL			/* undef for  U-BOOT 1.1.4 */
+//#define CONFIG_FPGA_ASPEED	1
+#define CONFIG_ARM926EJS	1		/* This is an arm926ejs CPU */
+#define	CONFIG_ASPEED		1
+#define CONFIG_AST2400		1
+//#define CONFIG_AST1070		1
+//#define CONFIG_SYS_FLASH_CFI			/* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
+#define CONFIG_FLASH_SPI
+//#define CONFIG_2SPIFLASH			/* Boot SPI: CS2, 2nd SPI: CS0 */
+#undef CONFIG_2SPIFLASH
+#undef CONFIG_ASPEED_SLT
+#define CONFIG_FLASH_AST2300
+//#define CONFIG_FLASH_AST2300_DMA
+//#define CONFIG_FLASH_SPIx2_Dummy
+//#define CONFIG_FLASH_SPIx4_Dummy
+#define CONFIG_CRT_DISPLAY	1		/* undef if not support CRT */
+
+//#define CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_FBPLATFORM1
+
+/*
+ * DRAM Config
+ *
+ * 1. DRAM Size              //
+ *    CONFIG_DRAM_512MBIT    // 512M bit
+ *    CONFIG_DRAM_1GBIT      // 1G   bit (default)
+ *    CONFIG_DRAM_2GBIT      // 2G   bit
+ *    CONFIG_DRAM_4GBIT      // 4G   bit
+ * 2. DRAM Speed             //
+ *    CONFIG_DRAM_336        // 336MHz (DDR-667)
+ *    CONFIG_DRAM_408        // 408MHz (DDR-800) (default)
+ * 3. VGA Mode
+ *    CONFIG_CRT_DISPLAY     // define to disable VGA function
+ * 4. ECC Function enable
+ *    CONFIG_DRAM_ECC        // define to enable ECC function
+ * 5. UART Debug Message
+ *    CONFIG_DRAM_UART_OUT   // enable output message at UART5
+ *    CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
+ */
+
+//1. DRAM Size
+//#define    CONFIG_DRAM_512MBIT
+#define    CONFIG_DRAM_1GBIT
+//#define    CONFIG_DRAM_2GBIT
+//#define    CONFIG_DRAM_4GBIT
+//2. DRAM Speed
+//#define    CONFIG_DRAM_336
+#define    CONFIG_DRAM_408
+//3. VGA Mode
+//#define    CONFIG_CRT_DISPLAY
+//4. ECC Function enable
+//#define    CONFIG_DRAM_ECC
+//5. UART Debug Message
+#define    CONFIG_DRAM_UART_OUT
+//#define    CONFIG_DRAM_UART_38400
+
+
+
+/*
+ * Environment Config
+ */
+#define CONFIG_CMDLINE_TAG	 1		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+#define	CONFIG_BOOTARGS 	"debug console=ttyS0,57600n8 root=/dev/ram rw"
+#define CONFIG_UPDATE           "tftp 40800000 ast2400.scr; so 40800000'"
+
+#define CONFIG_BOOTDELAY	3		/* autoboot after 3 seconds	*/
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"autoboot in %d seconds (stop with 'Delete' key)...\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR	"\x1b\x5b\x33\x7e" /* 'Delete', ESC[3~ */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#ifdef CONFIG_FLASH_AST2300
+#define CONFIG_BOOTCOMMAND	"bootm 20080000 20300000"
+#else
+#ifdef	CONFIG_SYS_FLASH_CFI
+#define CONFIG_BOOTCOMMAND	"bootm 10080000 10300000"
+#else
+#define CONFIG_BOOTCOMMAND	"bootm 14080000 14300000"
+#endif
+#endif
+#define CONFIG_BOOTFILE		"all.bin"
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NETTEST
+#define CONFIG_CMD_SLT
+
+/*
+ * CPU Setting
+ */
+#define CPU_CLOCK_RATE		18000000	/* 16.5 MHz clock for the ARM core */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 768*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Stack sizes,  The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+
+/*
+ * Memory Configuration
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		  0x40000000 	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x8000000 	/* 128 MB */
+
+#define CONFIG_SYS_SDRAM_BASE	0x40000000
+
+/*
+ * FLASH Configuration
+ */
+#ifdef CONFIG_SYS_FLASH_CFI				/* NOR Flash */
+
+#ifdef CONFIG_FLASH_AST2300
+#define PHYS_FLASH_1			0x20000000 	/* Flash Bank #1 */
+#else
+#define PHYS_FLASH_1			0x10000000 	/* Flash Bank #1 */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_FLASH_BANKS_LIST 	{ PHYS_FLASH_1 }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 	1
+#define CONFIG_SYS_MAX_FLASH_SECT	(256)		/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET					0x60000 	/* environment starts here  */
+#define CONFIG_ENV_SIZE					0x20000 	/* Total Size of Environment Sector */
+
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#else						/* SPI Flash */
+
+#ifdef CONFIG_FLASH_AST2300
+#define PHYS_FLASH_1		0x20000000 	/* Flash Bank #1 */
+#else
+#define PHYS_FLASH_1		0x14000000 	/* Flash Bank #1 */
+#define PHYS_FLASH_2		0x14800000 	/* Flash Bank #2 */
+#define PHYS_FLASH_2_BASE	0x10000000
+#endif
+
+#ifdef CONFIG_2SPIFLASH
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_2_BASE
+#define CONFIG_FLASH_BANKS_LIST 	{ PHYS_FLASH_1, PHYS_FLASH_2 }
+#define CONFIG_SYS_MAX_FLASH_BANKS 	2
+#define CONFIG_SYS_MAX_FLASH_SECT	(1024)		/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_OFFSET		0x7F0000 	/* environment starts here  */
+#define CONFIG_ENV_SIZE			0x010000 	/* Total Size of Environment Sector */
+#else
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_FLASH_BANKS_LIST 	{ PHYS_FLASH_1 }
+#define CONFIG_SYS_MAX_FLASH_BANKS 	1
+#define CONFIG_SYS_MAX_FLASH_SECT	(1024)		/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_OFFSET		0x60000 	/* environment starts here  */
+#define CONFIG_ENV_SIZE			0x20000 	/* Total Size of Environment Sector */
+#define CONFIG_ASPEED_WRITE_DEFAULT_ENV
+#endif
+
+#endif
+
+#define __LITTLE_ENDIAN                 1
+
+#define CONFIG_MONITOR_BASE		TEXT_BASE
+#define CONFIG_MONITOR_LEN		(192 << 10)
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ) 	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ) 	/* Timeout for Flash Write */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+
+#define CONFIG_SYS_PROMPT		"boot# " 	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x40000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x44FFFFFF	/* 256 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x43000000	/* default load address */
+
+#define CONFIG_SYS_TIMERBASE		0x1E782000	/* use timer 1 */
+#define CONFIG_SYS_HZ			      1000
+#define CONFIG_ASPEED_TIMER_CLK (1*1000*1000) /* use external clk (1M) */
+
+/*
+ * Serial Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		24000000
+#define CONFIG_SYS_NS16550_COM1		0x1e783000
+#define CONFIG_SYS_NS16550_COM2		0x1e784000
+#define CONFIG_SYS_NS16550_COM3		0x1e78e000
+#define	CONFIG_SYS_LOADS_BAUD_CHANGE
+#define CONFIG_CONS_INDEX		2
+#define CONFIG_BAUDRATE			57600
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_ASPEED_COM 0x1e784000 // COM2(UART5)
+#define CONFIG_ASPEED_COM_IER (CONFIG_ASPEED_COM + 0x4)
+#define CONFIG_ASPEED_COM_IIR (CONFIG_ASPEED_COM + 0x8)
+#define CONFIG_ASPEED_COM_LCR (CONFIG_ASPEED_COM + 0xc)
+
+/*
+ * USB device configuration
+ */
+/*
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+
+#define CONFIG_USBD_VENDORID		0x1234
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Siemens"
+#define CONFIG_USBD_PRODUCT_NAME	"SX1"
+*/
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_DRIVER_ASPEED_I2C
+
+/*
+* EEPROM configuration
+*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 	0xa0
+
+#define __BYTE_ORDER __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN_BITFIELD
+
+/*
+ * NIC configuration
+ */
+#define CONFIG_ASPEEDNIC
+#define CONFIG_NET_MULTI
+#define CONFIG_MAC1_ENABLE
+//#define CONFIG_MAC1_PHY_LINK_INTERRUPT
+//#define CONFIG_MAC2_ENABLE
+//#define CONFIG_MAC2_PHY_LINK_INTERRUPT
+/*
+*-------------------------------------------------------------------------------
+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
+* inform kernel driver.
+* The meanings of the 2 bits are:
+* 00(0): Dedicated PHY
+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
+* 11: Reserved
+*
+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
+* 0: Dedicated PHY
+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
+* 3: Reserved
+*-------------------------------------------------------------------------------
+*/
+#define CONFIG_MAC1_PHY_SETTING		2
+#define CONFIG_MAC2_PHY_SETTING		0
+#define CONFIG_ASPEED_MAC_NUMBER  1
+#define CONFIG_ASPEED_MAC_CONFIG  1 // config MAC1
+#define _PHY_SETTING_CONCAT(mac) CONFIG_MAC##mac##_PHY_SETTING
+#define _GET_MAC_PHY_SETTING(mac) _PHY_SETTING_CONCAT(mac)
+#define CONFIG_ASPEED_MAC_PHY_SETTING \
+  _GET_MAC_PHY_SETTING(CONFIG_ASPEED_MAC_CONFIG)
+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY	0x2255
+#define CONFIG_RANDOM_MACADDR
+//#define CONFIG_GATEWAYIP 192.168.0.1
+//#define CONFIG_NETMASK   255.255.255.0
+//#define CONFIG_IPADDR    192.168.0.45
+//#define CONFIG_SERVERIP  192.168.0.81
+
+/*
+ * SLT
+ */
+/*
+#define CONFIG_SLT
+#define CFG_CMD_SLT		(CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
+*/
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_ASPEED_ENABLE_WATCHDOG
+#define CONFIG_ASPEED_WATCHDOG_TIMEOUT (5*60) // 5m
+
+#endif	/* __CONFIG_H */
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/fbyosemite.h b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/fbyosemite.h
new file mode 100644
index 0000000..73a3cf9
--- /dev/null
+++ b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/fbyosemite.h
@@ -0,0 +1,353 @@
+/*
+ * Copyright 2015-present Facebook. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Uncommit the following line to enable JTAG in u-boot */
+//#define CONFIG_ASPEED_ENABLE_JTAG
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+//#define CONFIG_INIT_CRITICAL			/* define for U-BOOT 1.1.1 */
+#undef  CONFIG_INIT_CRITICAL			/* undef for  U-BOOT 1.1.4 */
+//#define CONFIG_FPGA_ASPEED	1
+#define CONFIG_ARM926EJS	1		/* This is an arm926ejs CPU */
+#define	CONFIG_ASPEED		1
+#define CONFIG_AST2400		1
+//#define CONFIG_AST1070		1
+//#define CONFIG_SYS_FLASH_CFI			/* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
+#define CONFIG_FLASH_SPI
+//#define CONFIG_2SPIFLASH			/* Boot SPI: CS2, 2nd SPI: CS0 */
+#undef CONFIG_2SPIFLASH
+#undef CONFIG_ASPEED_SLT
+#define CONFIG_FLASH_AST2300
+//#define CONFIG_FLASH_AST2300_DMA
+//#define CONFIG_FLASH_SPIx2_Dummy
+//#define CONFIG_FLASH_SPIx4_Dummy
+#define CONFIG_CRT_DISPLAY	1		/* undef if not support CRT */
+
+//#define CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_YOSEMITE
+
+/*
+ * DRAM Config
+ *
+ * 1. DRAM Size              //
+ *    CONFIG_DRAM_512MBIT    // 512M bit
+ *    CONFIG_DRAM_1GBIT      // 1G   bit (default)
+ *    CONFIG_DRAM_2GBIT      // 2G   bit
+ *    CONFIG_DRAM_4GBIT      // 4G   bit
+ * 2. DRAM Speed             //
+ *    CONFIG_DRAM_336        // 336MHz (DDR-667)
+ *    CONFIG_DRAM_408        // 408MHz (DDR-800) (default)
+ * 3. VGA Mode
+ *    CONFIG_CRT_DISPLAY     // define to disable VGA function
+ * 4. ECC Function enable
+ *    CONFIG_DRAM_ECC        // define to enable ECC function
+ * 5. UART Debug Message
+ *    CONFIG_DRAM_UART_OUT   // enable output message at UART5
+ *    CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
+ */
+
+//1. DRAM Size
+//#define    CONFIG_DRAM_512MBIT
+#define    CONFIG_DRAM_1GBIT
+//#define    CONFIG_DRAM_2GBIT
+//#define    CONFIG_DRAM_4GBIT
+//2. DRAM Speed
+//#define    CONFIG_DRAM_336
+#define    CONFIG_DRAM_408
+//3. VGA Mode
+//#define    CONFIG_CRT_DISPLAY
+//4. ECC Function enable
+//#define    CONFIG_DRAM_ECC
+//5. UART Debug Message
+#define    CONFIG_DRAM_UART_OUT
+//#define    CONFIG_DRAM_UART_38400
+
+
+
+/*
+ * Environment Config
+ */
+#define CONFIG_CMDLINE_TAG	 1		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+#define	CONFIG_BOOTARGS 	"debug console=ttyS0,57600n8 root=/dev/ram rw"
+#define CONFIG_UPDATE           "tftp 40800000 ast2400.scr; so 40800000'"
+
+#define CONFIG_BOOTDELAY	3		/* autoboot after 3 seconds	*/
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"autoboot in %d seconds (stop with 'Delete' key)...\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR	"\x1b\x5b\x33\x7e" /* 'Delete', ESC[3~ */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#ifdef CONFIG_FLASH_AST2300
+#define CONFIG_BOOTCOMMAND	"bootm 20080000 20300000"
+#else
+#ifdef	CONFIG_SYS_FLASH_CFI
+#define CONFIG_BOOTCOMMAND	"bootm 10080000 10300000"
+#else
+#define CONFIG_BOOTCOMMAND	"bootm 14080000 14300000"
+#endif
+#endif
+#define CONFIG_BOOTFILE		"all.bin"
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NETTEST
+#define CONFIG_CMD_SLT
+
+/*
+ * CPU Setting
+ */
+#define CPU_CLOCK_RATE		18000000	/* 16.5 MHz clock for the ARM core */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 768*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Stack sizes,  The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+
+/*
+ * Memory Configuration
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		  0x40000000 	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x8000000 	/* 128 MB */
+
+#define CONFIG_SYS_SDRAM_BASE	0x40000000
+
+/*
+ * FLASH Configuration
+ */
+#ifdef CONFIG_SYS_FLASH_CFI				/* NOR Flash */
+
+#ifdef CONFIG_FLASH_AST2300
+#define PHYS_FLASH_1			0x20000000 	/* Flash Bank #1 */
+#else
+#define PHYS_FLASH_1			0x10000000 	/* Flash Bank #1 */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_FLASH_BANKS_LIST 	{ PHYS_FLASH_1 }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 	1
+#define CONFIG_SYS_MAX_FLASH_SECT	(256)		/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET					0x60000 	/* environment starts here  */
+#define CONFIG_ENV_SIZE					0x20000 	/* Total Size of Environment Sector */
+
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#else						/* SPI Flash */
+
+#ifdef CONFIG_FLASH_AST2300
+#define PHYS_FLASH_1		0x20000000 	/* Flash Bank #1 */
+#else
+#define PHYS_FLASH_1		0x14000000 	/* Flash Bank #1 */
+#define PHYS_FLASH_2		0x14800000 	/* Flash Bank #2 */
+#define PHYS_FLASH_2_BASE	0x10000000
+#endif
+
+#ifdef CONFIG_2SPIFLASH
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_2_BASE
+#define CONFIG_FLASH_BANKS_LIST 	{ PHYS_FLASH_1, PHYS_FLASH_2 }
+#define CONFIG_SYS_MAX_FLASH_BANKS 	2
+#define CONFIG_SYS_MAX_FLASH_SECT	(1024)		/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_OFFSET		0x7F0000 	/* environment starts here  */
+#define CONFIG_ENV_SIZE			0x010000 	/* Total Size of Environment Sector */
+#else
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_FLASH_BANKS_LIST 	{ PHYS_FLASH_1 }
+#define CONFIG_SYS_MAX_FLASH_BANKS 	1
+#define CONFIG_SYS_MAX_FLASH_SECT	(1024)		/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_OFFSET		0x60000 	/* environment starts here  */
+#define CONFIG_ENV_SIZE			0x20000 	/* Total Size of Environment Sector */
+#define CONFIG_ASPEED_WRITE_DEFAULT_ENV
+#endif
+
+#endif
+
+#define __LITTLE_ENDIAN                 1
+
+#define CONFIG_MONITOR_BASE		TEXT_BASE
+#define CONFIG_MONITOR_LEN		(192 << 10)
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ) 	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ) 	/* Timeout for Flash Write */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+
+#define CONFIG_SYS_PROMPT		"boot# " 	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x40000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x44FFFFFF	/* 256 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x43000000	/* default load address */
+
+#define CONFIG_SYS_TIMERBASE		0x1E782000	/* use timer 1 */
+#define CONFIG_SYS_HZ			      1000
+#define CONFIG_ASPEED_TIMER_CLK (1*1000*1000) /* use external clk (1M) */
+
+/*
+ * Serial Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		24000000
+#define CONFIG_SYS_NS16550_COM1		0x1e783000
+#define CONFIG_SYS_NS16550_COM2		0x1e784000
+#define CONFIG_SYS_NS16550_COM3		0x1e78e000
+#define	CONFIG_SYS_LOADS_BAUD_CHANGE
+#define CONFIG_CONS_INDEX		2
+#define CONFIG_BAUDRATE			57600
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_ASPEED_COM 0x1e784000 // COM2(UART5)
+#define CONFIG_ASPEED_COM_IER (CONFIG_ASPEED_COM + 0x4)
+#define CONFIG_ASPEED_COM_IIR (CONFIG_ASPEED_COM + 0x8)
+#define CONFIG_ASPEED_COM_LCR (CONFIG_ASPEED_COM + 0xc)
+
+/*
+ * USB device configuration
+ */
+/*
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+
+#define CONFIG_USBD_VENDORID		0x1234
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Siemens"
+#define CONFIG_USBD_PRODUCT_NAME	"SX1"
+*/
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_DRIVER_ASPEED_I2C
+
+/*
+* EEPROM configuration
+*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 	0xa0
+
+#define __BYTE_ORDER __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN_BITFIELD
+
+/*
+ * NIC configuration
+ */
+#define CONFIG_ASPEEDNIC
+#define CONFIG_NET_MULTI
+#define CONFIG_MAC1_ENABLE
+//#define CONFIG_MAC1_PHY_LINK_INTERRUPT
+//#define CONFIG_MAC2_ENABLE
+//#define CONFIG_MAC2_PHY_LINK_INTERRUPT
+/*
+*-------------------------------------------------------------------------------
+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
+* inform kernel driver.
+* The meanings of the 2 bits are:
+* 00(0): Dedicated PHY
+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
+* 11: Reserved
+*
+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
+* 0: Dedicated PHY
+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
+* 3: Reserved
+*-------------------------------------------------------------------------------
+*/
+#define CONFIG_MAC1_PHY_SETTING		2
+#define CONFIG_MAC2_PHY_SETTING		0
+#define CONFIG_ASPEED_MAC_NUMBER  1
+#define CONFIG_ASPEED_MAC_CONFIG  1 // config MAC1
+#define _PHY_SETTING_CONCAT(mac) CONFIG_MAC##mac##_PHY_SETTING
+#define _GET_MAC_PHY_SETTING(mac) _PHY_SETTING_CONCAT(mac)
+#define CONFIG_ASPEED_MAC_PHY_SETTING \
+  _GET_MAC_PHY_SETTING(CONFIG_ASPEED_MAC_CONFIG)
+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY	0x2255
+#define CONFIG_RANDOM_MACADDR
+//#define CONFIG_GATEWAYIP 192.168.0.1
+//#define CONFIG_NETMASK   255.255.255.0
+//#define CONFIG_IPADDR    192.168.0.45
+//#define CONFIG_SERVERIP  192.168.0.81
+
+/*
+ * SLT
+ */
+/*
+#define CONFIG_SLT
+#define CFG_CMD_SLT		(CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
+*/
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_ASPEED_ENABLE_WATCHDOG
+#define CONFIG_ASPEED_WATCHDOG_TIMEOUT (5*60) // 5m
+
+#endif	/* __CONFIG_H */
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/wedge100.h b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/wedge100.h
new file mode 100644
index 0000000..1aa3260
--- /dev/null
+++ b/meta-aspeed/recipes-bsp/u-boot/files/u-boot-v2013.07/include/configs/wedge100.h
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2004-present Facebook. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Uncommit the following line to enable JTAG in u-boot */
+//#define CONFIG_ASPEED_ENABLE_JTAG
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+//#define CONFIG_INIT_CRITICAL			/* define for U-BOOT 1.1.1 */
+#undef  CONFIG_INIT_CRITICAL			/* undef for  U-BOOT 1.1.4 */
+//#define CONFIG_FPGA_ASPEED	1
+#define CONFIG_ARM926EJS	1		/* This is an arm926ejs CPU */
+#define	CONFIG_ASPEED		1
+#define CONFIG_AST2400		1
+#define CONFIG_WEDGE100		1
+//#define CONFIG_AST1070		1
+//#define CONFIG_SYS_FLASH_CFI			/* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
+#define CONFIG_FLASH_SPI
+//#define CONFIG_2SPIFLASH			/* Boot SPI: CS2, 2nd SPI: CS0 */
+#undef CONFIG_2SPIFLASH
+#undef CONFIG_ASPEED_SLT
+#define CONFIG_FLASH_AST2300
+//#define CONFIG_FLASH_AST2300_DMA
+//#define CONFIG_FLASH_SPIx2_Dummy
+//#define CONFIG_FLASH_SPIx4_Dummy
+#define CONFIG_CRT_DISPLAY	1		/* undef if not support CRT */
+
+//#define CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+#define CONFIG_MISC_INIT_R
+
+/*
+ * DRAM Config
+ *
+ * 1. DRAM Size              //
+ *    CONFIG_DRAM_512MBIT    // 512M bit
+ *    CONFIG_DRAM_1GBIT      // 1G   bit (default)
+ *    CONFIG_DRAM_2GBIT      // 2G   bit
+ *    CONFIG_DRAM_4GBIT      // 4G   bit
+ * 2. DRAM Speed             //
+ *    CONFIG_DRAM_336        // 336MHz (DDR-667)
+ *    CONFIG_DRAM_408        // 408MHz (DDR-800) (default)
+ * 3. VGA Mode
+ *    CONFIG_CRT_DISPLAY     // define to disable VGA function
+ * 4. ECC Function enable
+ *    CONFIG_DRAM_ECC        // define to enable ECC function
+ * 5. UART Debug Message
+ *    CONFIG_DRAM_UART_OUT   // enable output message at UART5
+ *    CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
+ */
+
+//1. DRAM Size
+//#define    CONFIG_DRAM_512MBIT
+#define    CONFIG_DRAM_1GBIT
+//#define    CONFIG_DRAM_2GBIT
+//#define    CONFIG_DRAM_4GBIT
+//2. DRAM Speed
+//#define    CONFIG_DRAM_336
+#define    CONFIG_DRAM_408
+//3. VGA Mode
+//#define    CONFIG_CRT_DISPLAY
+//4. ECC Function enable
+//#define    CONFIG_DRAM_ECC
+//5. UART Debug Message
+#define    CONFIG_DRAM_UART_OUT
+//#define    CONFIG_DRAM_UART_38400
+
+
+
+/*
+ * Environment Config
+ */
+#define CONFIG_CMDLINE_TAG	 1		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+#define	CONFIG_BOOTARGS 	"debug console=ttyS2,9600n8 root=/dev/ram rw"
+#define CONFIG_UPDATE           "tftp 40800000 ast2400.scr; so 40800000'"
+
+#define CONFIG_BOOTDELAY	3		/* autoboot after 3 seconds	*/
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"autoboot in %d seconds (stop with 'Delete' key)...\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR	"\x1b\x5b\x33\x7e" /* 'Delete', ESC[3~ */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#ifdef CONFIG_FLASH_AST2300
+#define CONFIG_BOOTCOMMAND	"bootm 20080000 20300000"
+#else
+#ifdef	CONFIG_SYS_FLASH_CFI
+#define CONFIG_BOOTCOMMAND	"bootm 10080000 10300000"
+#else
+#define CONFIG_BOOTCOMMAND	"bootm 14080000 14300000"
+#endif
+#endif
+#define CONFIG_BOOTFILE		"all.bin"
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NETTEST
+#define CONFIG_CMD_SLT
+
+/*
+ * CPU Setting
+ */
+#define CPU_CLOCK_RATE		18000000	/* 16.5 MHz clock for the ARM core */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 768*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Stack sizes,  The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+
+/*
+ * Memory Configuration
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		  0x40000000 	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x10000000 	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE	0x40000000
+
+/*
+ * FLASH Configuration
+ */
+#ifdef CONFIG_SYS_FLASH_CFI				/* NOR Flash */
+
+#ifdef CONFIG_FLASH_AST2300
+#define PHYS_FLASH_1			0x20000000 	/* Flash Bank #1 */
+#else
+#define PHYS_FLASH_1			0x10000000 	/* Flash Bank #1 */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_FLASH_BANKS_LIST 	{ PHYS_FLASH_1 }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 	1
+#define CONFIG_SYS_MAX_FLASH_SECT	(256)		/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET					0x60000 	/* environment starts here  */
+#define CONFIG_ENV_SIZE					0x20000 	/* Total Size of Environment Sector */
+
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#else						/* SPI Flash */
+
+#ifdef CONFIG_FLASH_AST2300
+#define PHYS_FLASH_1		0x20000000 	/* Flash Bank #1 */
+#else
+#define PHYS_FLASH_1		0x14000000 	/* Flash Bank #1 */
+#define PHYS_FLASH_2		0x14800000 	/* Flash Bank #2 */
+#define PHYS_FLASH_2_BASE	0x10000000
+#endif
+
+#ifdef CONFIG_2SPIFLASH
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_2_BASE
+#define CONFIG_FLASH_BANKS_LIST 	{ PHYS_FLASH_1, PHYS_FLASH_2 }
+#define CONFIG_SYS_MAX_FLASH_BANKS 	2
+#define CONFIG_SYS_MAX_FLASH_SECT	(1024)		/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_OFFSET		0x7F0000 	/* environment starts here  */
+#define CONFIG_ENV_SIZE			0x010000 	/* Total Size of Environment Sector */
+#else
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_FLASH_BANKS_LIST 	{ PHYS_FLASH_1 }
+#define CONFIG_SYS_MAX_FLASH_BANKS 	1
+#define CONFIG_SYS_MAX_FLASH_SECT	(1024)		/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_OFFSET		0x60000 	/* environment starts here  */
+#define CONFIG_ENV_SIZE			0x20000 	/* Total Size of Environment Sector */
+#define CONFIG_ASPEED_WRITE_DEFAULT_ENV
+#endif
+
+#endif
+
+#define __LITTLE_ENDIAN                 1
+
+#define CONFIG_MONITOR_BASE		TEXT_BASE
+#define CONFIG_MONITOR_LEN		(192 << 10)
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ) 	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ) 	/* Timeout for Flash Write */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+
+#define CONFIG_SYS_PROMPT		"boot# " 	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x40000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x44FFFFFF	/* 256 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x43000000	/* default load address */
+
+#define CONFIG_SYS_TIMERBASE		0x1E782000	/* use timer 1 */
+#define CONFIG_SYS_HZ			      1000
+#define CONFIG_ASPEED_TIMER_CLK (1*1000*1000) /* use external clk (1M) */
+
+/*
+ * Serial Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		24000000
+#define CONFIG_SYS_NS16550_COM1		0x1e783000
+#define CONFIG_SYS_NS16550_COM2		0x1e784000
+#define CONFIG_SYS_NS16550_COM3		0x1e78e000
+#define	CONFIG_SYS_LOADS_BAUD_CHANGE
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_BAUDRATE			9600
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_ASPEED_COM 0x1e78e000 // COM3
+#define CONFIG_ASPEED_COM_IER (CONFIG_ASPEED_COM + 0x4)
+#define CONFIG_ASPEED_COM_IIR (CONFIG_ASPEED_COM + 0x8)
+#define CONFIG_ASPEED_COM_LCR (CONFIG_ASPEED_COM + 0xc)
+
+/*
+ * USB device configuration
+ */
+/*
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+
+#define CONFIG_USBD_VENDORID		0x1234
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Siemens"
+#define CONFIG_USBD_PRODUCT_NAME	"SX1"
+*/
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_DRIVER_ASPEED_I2C
+
+/*
+* EEPROM configuration
+*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 	0xa0
+
+#define __BYTE_ORDER __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN_BITFIELD
+
+/*
+ * NIC configuration
+ */
+#define CONFIG_ASPEEDNIC
+#define CONFIG_NET_MULTI
+#define CONFIG_MAC1_PHY_LINK_INTERRUPT
+#define CONFIG_MAC2_ENABLE
+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
+/*
+*-------------------------------------------------------------------------------
+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
+* inform kernel driver.
+* The meanings of the 2 bits are:
+* 00(0): Dedicated PHY
+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
+* 11: Reserved
+*
+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
+* 0: Dedicated PHY
+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
+* 3: Reserved
+*-------------------------------------------------------------------------------
+*/
+#define CONFIG_MAC1_PHY_SETTING		0
+#define CONFIG_MAC2_PHY_SETTING		0
+#define CONFIG_ASPEED_MAC_NUMBER  2
+#define CONFIG_ASPEED_MAC_CONFIG  2 // config MAC2
+#define _PHY_SETTING_CONCAT(mac) CONFIG_MAC##mac##_PHY_SETTING
+#define _GET_MAC_PHY_SETTING(mac) _PHY_SETTING_CONCAT(mac)
+#define CONFIG_ASPEED_MAC_PHY_SETTING \
+  _GET_MAC_PHY_SETTING(CONFIG_ASPEED_MAC_CONFIG)
+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY	0x2255
+#define CONFIG_RANDOM_MACADDR
+//#define CONFIG_GATEWAYIP 192.168.0.1
+//#define CONFIG_NETMASK   255.255.255.0
+//#define CONFIG_IPADDR    192.168.0.45
+//#define CONFIG_SERVERIP  192.168.0.81
+
+/*
+ * SLT
+ */
+/*
+#define CONFIG_SLT
+#define CFG_CMD_SLT		(CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
+*/
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_ASPEED_ENABLE_WATCHDOG
+#define CONFIG_ASPEED_WATCHDOG_TIMEOUT (5*60) // 5m
+#define CONFIG_ASPEED_ENABLE_DUAL_BOOT_WATCHDOG
+#define CONFIG_ASPEED_WATCHDOG_DUAL_BOOT_TIMEOUT \
+  (CONFIG_ASPEED_WATCHDOG_TIMEOUT - 5)
+
+#endif	/* __CONFIG_H */
-- 
1.8.1